Since there is a proceeding miniaturization of the structures on microchips to increase packing density, reduce power consumption, and increase switching speeds, the conductors for wiring are moving closer and closer together in vertical and horizontal direction. To isolate the conductors from each other additional films like silicon dioxide SiO2 have to be deposited as an interlayer dielectric (ILD).
If conductors run parallel or cross each other on different layers upon another, parasitic capacities are created. The conductors represent the electrodes while the SiO2 in-between is the dielectric.
Traditional capacitor and crossing of two conductors
The capacity C is given by:
Where d stands for the distance of the electrodes, A is the area of the electrodes, ε0 the vacuum permittivity and εr (often κ (Kappa) or simplified k) the relative static permittivity of the ILD.
The value of the parasitic capacity influences the electric properties such as the switching speed or the power consumption of a chip, and therefore one tries to decrease C. Theoretical this can be done if ε0, εr and A are decreased or if d is increased. However, as mentioned above d is getting smaller and smaller, A is preset by electrical requirements and ε0 is a physical constant. Thus the capacity can only be reduced by decreasing εr.
To sum it up, one needs dielectrics with a low εr: low-k.
The traditional dielectric, SiO2, has a relative permittivity of about 4. Low-k referes to materials whose εr is less than that of silicon dioxide. Beyond that there will be Ultra-Low-k materials with an εr of less than 2.4. The permittivity referes to the polarization (dislocation of charge carriers in the insulator) in the dielectric and is the factor by which the charge of a capacitor is increased relative to vacuum or by which the electric field inside the capacitor is weakened.
To reduce the permittivity there are basically two possibilities:
- the polarizability of bonds inside the dielectric has to be decreased
- the quantity of bonds has to be reduced by introduction of porosity in the dielectric
The polarizability can be decreased by materials with less polar groups. Candidates are fluorined (FSG, εr 3.6) or organic (OSG) silicon oxides. However, for smaller and smaller structures this approach isn't sufficient, thus porous films have been introduced. By introduction of porosity there is "empty space" inside the ILD which has - in case of air - a permittivity of about 1, and therefore εr is reduced for the entire layer. The pores can be introduced by adding polymers which are expelled later by thermal annealing. In case of silicon dioxide one needs about 50 % of pores in the material to achieve a permittivity of 2. If a dielectric is used whose permittivity is 2.5 without porosity, only 22 % pores have to be introduced to achieve a permittivity of 2.
Relative static permittivity against porosity
However, there are several issues to overcome, if one wants to bring in such new materials into semiconductor fabrication.
Due to porosity the density is reduced which results in a lower mechanical resistance. In addition process gases or copper can diffuse into the ILD and cause damage and thus increasing the permittivity or leakage. To counteract this issues, the pores have to be distributed evenly and must not be in contact with each other. To avoid a diffusion of copper, a thin barrier layer has to be deposited in a seperate process or the pores at the surface have to be closed by ion bombardment.
Like the photoresist used for manufacturing, the organic ILD is composed of hydrocarbon. If the resist is stripped in an ash process, the ILD is affected as well. To avoid this issue, additional layers (like silicon nitride as hardmask) have to be introduced in the film stack.
Overview of organic silicon oxides