The damascene process makes use of existent interlayer dielectrics in which the vias and trenches for conduction paths are etched. Subsequent, copper is deposited by CVD, PVD + reflow, or in electrochemical/galvanically processes. Finally, the copper is planished by chemical mechanical polishing (CMP).
The damascene process can be seperated into the single and dual damascene process and the latter can be seperated further into the VFTL (VIA First Trench Last) and the TFVL approach (Trench First VIA Last).
In the following, both the TFVL as well as the VFTL process are described.
Dual damascene: Trench First VIA Last: On top of the wafer (in this example on an existing copper layer) different layers are deposited which act as protection, isolation or passivation layers. As an etch stop and protection against gaseous molecules, silicon nitride (SiN) or silicon carbide (SiC) can be used. As interlayer dielectric (ILD), materials with a low relative static permittivity are used, like silicon dioxide SiO2. Upon a resist mask is patterned.
1. The wafer is coated with a resist layer which is structured in photolithography.
2. The hardmask (SiN) and the ILD are etched in a anisotropic dry etch process until the first etch stop layer (SiN) is reached.
The resist is removed and the trench for the conduction path is finished.
The hardmask on top protects the ILD during the resist ash. This is necessary since the ILD has a similar composition as the resist and therefore is affected by the same process gases. In addition the hardmask acts as a barrier layer during terminal CMP.
3. Next a new resist layer is deposited and structured.
4. Finally the vias are opened in an anisotropic etch process.
With a low energetic etch process, the bottom etch stop is opened to avoid sputtering of the copper beneath which could deposit on the sidewalls and diffuse into the ILD. The resist is removed and a thin layer of tantalum is deposited as a barrier which prevents later deposited copper from diffusing into the ILD.
5. A thin copper layer acts as a seed layer, so that the vias and trenches can be filled in a galvanically process.
6. The deposited copper is planished in a CMP process.
The big disadvantage of this process is the thick resist layer which is deposited after the trenches have been etched (3). To etch the tiny vias in such a thick resist layer is very difficult. For this reason the TFVL approach is done at larger structures only.
Dual damascene: VIA First Trench Last: The VFTL approach is alike the TFVL process but now the vias are created first.
1. A resist layer to form the vias is structured and the vias transferred into the ILD by an anisotropic etch process till the bottom etch stop layer is reached. To prevent copper from being sputtered out of the metallization beneath, the etch stop must not be opened.
2. Subsequent the resist is removed, a new resist layer is patterend which represents the trenches; also the previously opened vias are filled with resist.
3. During the trench etch, the bottom etch stop is covered by resist.
Next the bottom etch stop is opened in a low energetic process and a tantalum barrier and a copper seed layer are deposited.
4. After the copper deposition, the metal is planished in a CMP process.
In the single damascene process, the via layer and the trench layer are deposited and structured one after each other, so that there are more process steps needed (ILD deposition → VIA structuring → copper deposition → planarization → ILD deposition → trench structuring → copper deposition → planarization).