Semiconductor Technology from A to Z

Everything about semiconductors and wafer fabrication

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Fundamentals
- The atomic structure
  - The Atomic Model
  - Orders of Magnitude
- The elements, the periodic table
  - The Elements
  - The Periodic Table of the Elements
- Chemical bonds
- Conductors – Insulators – Semiconductors
- Doping: n- and p-semiconductors
- The p-n junction
  - The p-n Junction in Equilibrium
  - The p-n Junction with an Applied Voltage
- Transistors and Memory
Wafer Fabrication
- Silicon
- Production of raw silicon
- Fabrication of the single crystal
- The wafer
Oxidation
- Overview
  - Application of Oxide Layers
  - Properties of oxide layers
- Fabrication of oxide layers
  - Thermal oxidation
  - Oxidation by vapor deposition
- LOCOS technology
Deposition
- Plasma, the fourth aggregation state of a material
  - Plasma state
  - Plasma generation
- Chemical vapor deposition
- Physical deposition methods
Photolithography
- Exposure and resist coating
- Exposition methods
- Photoresist
  - Photoresist
  - Chemical composition
- Development and inspection
- Photomasks
- Optical Proximity Correction (OPC)
- DUV vs. EUV
- EUV Tool Technology
Wet Chemistry
- Etch processes
- Wet etching
- Wafer cleaning
Dry Etching
- Overview
- Dry etch processes
- Reactor Types
- Etching of Compound Semiconductors and High-k Materials
Doping Techniques
- Diffusion
- Ion Implantation
Metallization
- Requirements on metallization
- Aluminum technology
- Copper technology
- Metal semiconductor junction
- Chemical Mechanical Polishing (CMP)
- Wiring
Metrology
- Film thickness measurement
- Particle inspection
- CD Measurement
- Overlay Measurement
Wafer Test
- Wafer Test
- Final Test and Binning
Assembly
- Dicing
- Die Attach
- Bonding
- Encapsulation
Advanced Packaging / 3D Integration
- Limits of Classical Integration
- Through-Silicon Via (TSV)
- 2.5D Integration: The Interposer
- 3D Stacking
- Chiplets & Heterogeneous Integration
- Applications & Outlook
Reliability
- ESD Protection Structures
- Electromigration, TDDB and NBTI/PBTI
- Burn-in and HTOL Testing
- Automotive, Military, and Space Qualification
Devices
- Zener and Avalanche Diodes
- The Schottky Diode
- The Tunnel Diode
- Thyristors and Triacs
- Field-Effect Transistor Families: An Overview
- Field-effect transistors
  - Fundamentals
  - Fabrication of an n-Channel FET
- Construction of a FinFET
- The Junction FET (JFET)
- The Metal-Semiconductor FET (MESFET)
- Bipolar transistors
  - Fundamentals
  - Fabrication of an NPN Bipolar Transistor
- Characteristic Curves and Transistor Equations
- Si Power Devices (Power MOSFET, IGBT)
- CMOS vs. Bipolar
- Bulk vs. SOI
Digital technology
- From transistor to logic gate
  - The Transistor as a Switch
  - NMOS and PMOS Compared
  - The Inverter — the First Gate
  - Building NAND from Transistors
  - Building NOR from Transistors
  - Building AND from Transistors
  - Building OR from Transistors
  - Building XOR from Transistors
  - Logic Gates Overview
- The CMOS Fabrication Flow
  - Front-End and Back-End of Line
  - Wafer and Wells
  - Transistor Fabrication in the FEOL
  - Doping and Silicidation
  - Contacts
  - Metallization in the BEOL
  - The Flow at a Glance
- Arithmetic Circuits: Adders and Multipliers
  - The Full Adder as a Basic Building Block
  - Carry-Ripple vs. Carry-Lookahead Adders
  - Multipliers: From Array to Wallace Tree
- Sequential Logic: Flip-Flops, Latches, and Clock Trees
  - The SR Latch: The Simplest Bistable Element
  - Flip-Flop Types Overview: SR, JK, T, and D
  - Latches and Flip-Flops
  - The Clock Tree
  - Asynchronous Control Inputs and Scan Flip-Flops
- Static Timing Analysis: Setup and Hold Time
  - Fundamentals of Static Timing Analysis
  - The Setup Check
  - The Hold Check and the Role of Clock Skew
- Static and Dynamic Power Dissipation, Leakage Currents
  - Dynamic Power Dissipation
  - Static Power Dissipation and Leakage Currents
  - Power Reduction Techniques
- The SRAM Cell
  - Two Cross-Coupled Inverters as the Storage Core
  - The Access Transistors
  - Writing
  - From a Single Bit to an Array
  - Reading
- The DRAM Cell
  - A Capacitor Instead of Six Transistors
  - Access Transistor, Word Line, and Bit Line
  - Leakage and Charge Decay
  - The Refresh Cycle
  - The Sense Amplifier
  - DRAM versus SRAM
- DRAM Fabrication: The Trench Capacitor Process
  - General Structure and Operating Principle
  - Trench Capacitor Fabrication
  - Access Transistor and Interconnect Fabrication
- The Flash Memory Cell
  - Structure of the Floating-Gate Cell
  - Programming and Erasing
  - NOR vs. NAND Architecture
  - Multi-Level Cell (MLC/TLC)
  - Comparison: DRAM, SRAM, and Flash
- Circuit Layouts
  - From Schematic to Chip: EDA
  - From Schematic to Layout
  - Layer 1: Active Areas
  - Layer 2: Polysilicon
  - Layer 3: Contacts
  - Layer 4: Metal-1
  - Layer 5: Metal-2
  - Layer 6: Metal-3 — Complete
- Design Rules
  - Introduction & Motivation
  - Basic Rule Types
  - Lambda-based vs. Absolute Rules
  - Example Rule Set
  - Latchup and Well Rules
  - Antenna Rules
  - Density Rules (CMP)
  - Design Rule Check (DRC)
- Layout versus Schematic (LVS)
  - Introduction & Motivation
  - Netlist Extraction from the Layout
  - The Reference Netlist from the Schematic
  - The Comparison Algorithm
  - Typical Mismatches
  - LVS in the Design Flow
- Processor Architecture
  - Overview
  - Basic Architecture
  - Core Components
  - Memory Hierarchy
  - Clock, Pipelining and Parallelism
  - From Die to Chip
- Control Unit and Instruction Execution
  - Datapath and Control Unit: Who Does What
  - Opcode and the Fetch-Decode-Execute Cycle
  - Hardwired versus Microcoded Control Units
- CPU vs. GPU
  - Overview
  - Architectural Difference
  - Memory Hierarchy and Bandwidth
  - Application Areas
  - Comparison Table
- FPGA vs. ASIC: Synthesis Flow and HDL
  - Two Paths from Circuit Design to Silicon
  - Hardware Description Languages and the Synthesis Flow
  - When FPGA, When ASIC?
- Why New Memory Technologies?
  - The Limits of Flash
  - The Gap Between Working Memory and Mass Storage
- MRAM – Magnetoresistive RAM
  - The Tunnel Magnetoresistance Effect (TMR)
  - Structure of the Magnetic Tunnel Junction (MTJ)
  - STT-MRAM as Today's Standard Variant
  - Properties
- ReRAM – Resistive RAM
  - The Principle of Filament Formation
  - Set and Reset Operations
  - Material Systems
  - Properties and Challenges
- PCM – Phase-Change Memory
  - Amorphous vs. Crystalline State as the Storage Principle
  - The Chalcogenide Material GST
  - Writing by Heating and Quenching
  - Intel Optane as the Best-Known Example
- Comparison & Context
  - MRAM, ReRAM, PCM, and Flash Directly Compared
  - Applications and Outlook
Analog & Mixed-Signal Design
- Operational Amplifiers
- ADC Architectures
- DAC Architectures
- Bandgap References
- Comparators
- PLL – Phase-Locked Loop
- Voltage Regulators: LDOs and Switching Regulators
- Noise in Semiconductor Devices
Optoelectronics & Photonics
- Fundamentals of Optoelectronics
- Light-Emitting Diodes (LED)
- Laser Diodes
- Photodiodes & Photodetectors
- Integration & Applications
- Fabrication of Optoelectronic Devices
- Solar Cells
Micromechanics
- Introduction to MEMS
- Anisotropic Etching of Silicon
- Sacrificial Layer Technique
- Bulk vs. Surface Micromachining
- The MEMS Accelerometer
- The Microphone and Pressure Sensor
- DRIE: Deep Reactive Ion Etching
Compound Semiconductors
- Fundamentals & Material System
- Crystal Growth & Substrates
- SiC Power Devices
- GaN Power Devices
- Applications & System Comparison
- HEMT and HBT for RF Applications
- InP-Based Photonic Devices
How does it work?
- Fabrication Processes
- Devices & Digital Technology
- Optoelectronics
- Packaging & Other Topics