Semiconductor Technology from A to Z

All the circuit diagrams in this section — from the single transistor to the SRAM cell — were created using Electronic Design Automation (EDA): the software toolchain used to design integrated circuits today. An EDA schematic like the one shown here is more than an illustration — it's the input for the next design steps: simulation verifies the electrical behaviour, place & route generates the physical layout on the wafer, and verification checks that the two match. An SRAM cell is a particularly good example of this, because it's repeated identically millions of times on a modern chip — exactly the kind of regular, highly optimised structure that makes EDA tools indispensable.

Storing a single bit sounds like a trivial task at first — but it's actually one of the most common circuit blocks of all. Every processor cache, every register file consists of millions to billions of such cells. The SRAM cell (Static Random Access Memory) doesn't store its bit as charge on a capacitor like DRAM, but as the stable switching state of two cross-coupled inverters. As long as the supply voltage is present, the stored value is retained — no refresh needed, but also without DRAM's high packing density, since a single bit takes six transistors instead of one.

At the heart of the cell are two CMOS inverters (familiar from chapter 3: one PMOS as pull-up, one NMOS as pull-down), whose inputs and outputs are cross-connected — the output of one inverter drives the input of the other. This feedback creates two stable states: if node 1 is High, that forces the second inverter to hold node 0 Low, which in turn confirms the first inverter's node 1 stays High. The state stabilises itself, with no clock or refresh needed — hence "static". Flipping it requires writing against this feedback from outside with sufficient drive strength.

The two stored nodes 1 and 0 aren't connected directly to the cell's input/output lines, but each through its own NMOS access transistor to the bit lines BL and BL̄. Their gates are tied together to the word line (WL). When WL is Low, both access transistors are fully off — the cell is disconnected from the bit lines and holds its state in isolation. Only when WL is pulled High do both transistors turn on simultaneously, connecting node 1 to BL and node 0 to BL̄. This one shared word line is later used to address a whole row of cells in the memory array at once.

To write, BL and BL̄ are driven externally, low-impedance, to an inverted pair of levels (e.g. BL = 5 V, BL̄ = 0 V for a "1"), while WL is activated. The external drivers are deliberately made stronger than the cell's own feedback loop — they override the current state through the access transistors and force the inverters into the new, desired state. Once WL falls Low again, the two inverters hold the freshly written value on their own.

A cell's word line (WL) isn't wired individually — it runs through an entire row of neighbouring cells, and every cell in that row shares the same WL. Perpendicular to it, each bit-line pair (BL/BL̄) runs through every cell in a column. This forms a grid: only the cell at the intersection where WL is active and the matching bit lines are present is actually addressed during a write or read — every other cell in the same column stays isolated by its own, inactive word line, even though it hangs off the same bit lines. This row/column addressing lets a comparatively small number of lines individually address an array of millions of cells.

Before every read access, both bit lines are first precharged to a shared mid-level potential. Activating WL then pulls one of the two lines slightly toward the stored state through the cell's access transistors, while the other stays close to the precharge level — a small voltage differential builds up between BL and BL̄. A downstream sense amplifier detects even this tiny difference and amplifies it to a clean digital level. Importantly, the read itself only weakly disturbs the stored state — unlike DRAM, the cell's content is left unchanged.