Digital technology

01

From transistor to logic gate

• The Transistor as a Switch
• NMOS and PMOS Compared
• The Inverter — the First Gate
• Building NAND from Transistors
• Building NOR from Transistors
• Building AND from Transistors
• Building OR from Transistors
• Building XOR from Transistors
• Logic Gates Overview

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02

The CMOS Fabrication Flow

• Front-End and Back-End of Line
• Wafer and Wells
• Transistor Fabrication in the FEOL
• Doping and Silicidation
• Contacts
• Metallization in the BEOL
• The Flow at a Glance

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03

Arithmetic Circuits: Adders and Multipliers

• The Full Adder as a Basic Building Block
• Carry-Ripple vs. Carry-Lookahead Adders
• Multipliers: From Array to Wallace Tree

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04

Sequential Logic: Flip-Flops, Latches, and Clock Trees

• The SR Latch: The Simplest Bistable Element
• Flip-Flop Types Overview: SR, JK, T, and D
• Latches and Flip-Flops
• The Clock Tree
• Asynchronous Control Inputs and Scan Flip-Flops

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05

Static Timing Analysis: Setup and Hold Time

• Fundamentals of Static Timing Analysis
• The Setup Check
• The Hold Check and the Role of Clock Skew

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06

Static and Dynamic Power Dissipation, Leakage Currents

• Dynamic Power Dissipation
• Static Power Dissipation and Leakage Currents
• Power Reduction Techniques

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07

The SRAM Cell

• Two Cross-Coupled Inverters as the Storage Core
• The Access Transistors
• Writing
• From a Single Bit to an Array
• Reading

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08

The DRAM Cell

• A Capacitor Instead of Six Transistors
• Access Transistor, Word Line, and Bit Line
• Leakage and Charge Decay
• The Refresh Cycle
• The Sense Amplifier
• DRAM versus SRAM

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09

DRAM Fabrication: The Trench Capacitor Process

• General Structure and Operating Principle
• Trench Capacitor Fabrication
• Access Transistor and Interconnect Fabrication

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10

The Flash Memory Cell

• Structure of the Floating-Gate Cell
• Programming and Erasing
• NOR vs. NAND Architecture
• Multi-Level Cell (MLC/TLC)
• Comparison: DRAM, SRAM, and Flash

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11

Why New Memory Technologies?

• The Limits of Flash
• The Gap Between Working Memory and Mass Storage

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12

MRAM – Magnetoresistive RAM

• The Tunnel Magnetoresistance Effect (TMR)
• Structure of the Magnetic Tunnel Junction (MTJ)
• STT-MRAM as Today's Standard Variant
• Properties

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13

ReRAM – Resistive RAM

• The Principle of Filament Formation
• Set and Reset Operations
• Material Systems
• Properties and Challenges

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14

PCM – Phase-Change Memory

• Amorphous vs. Crystalline State as the Storage Principle
• The Chalcogenide Material GST
• Writing by Heating and Quenching
• Intel Optane as the Best-Known Example

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15

Comparison & Context

• MRAM, ReRAM, PCM, and Flash Directly Compared
• Applications and Outlook

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16

Circuit Layouts

• From Schematic to Chip: EDA
• From Schematic to Layout
• Layer 1: Active Areas
• Layer 2: Polysilicon
• Layer 3: Contacts
• Layer 4: Metal-1
• Layer 5: Metal-2
• Layer 6: Metal-3 — Complete

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17

Design Rules

• Introduction & Motivation
• Basic Rule Types
• Lambda-based vs. Absolute Rules
• Example Rule Set
• Latchup and Well Rules
• Antenna Rules
• Density Rules (CMP)
• Design Rule Check (DRC)

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18

Layout versus Schematic (LVS)

• Introduction & Motivation
• Netlist Extraction from the Layout
• The Reference Netlist from the Schematic
• The Comparison Algorithm
• Typical Mismatches
• LVS in the Design Flow

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19

Processor Architecture

• Overview
• Basic Architecture
• Core Components
• Memory Hierarchy
• Clock, Pipelining and Parallelism
• From Die to Chip

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20

Control Unit and Instruction Execution

• Datapath and Control Unit: Who Does What
• Opcode and the Fetch-Decode-Execute Cycle
• Hardwired versus Microcoded Control Units

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21

CPU vs. GPU

• Overview
• Architectural Difference
• Memory Hierarchy and Bandwidth
• Application Areas
• Comparison Table

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22

FPGA vs. ASIC: Synthesis Flow and HDL

• Two Paths from Circuit Design to Silicon
• Hardware Description Languages and the Synthesis Flow
• When FPGA, When ASIC?

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