ADC Architectures

An analog-to-digital converter (ADC) converts a continuous-time, continuous-amplitude signal into a sequence of discrete numerical values. This process consists of two separate steps: sampling in time and quantization of the amplitude.

According to the Nyquist–Shannon sampling theorem, the sampling frequency must be at least twice the highest frequency component contained in the signal in order to reconstruct it without loss of information. Otherwise, aliasing produces indistinguishable mirror frequencies – in practice, an analog anti-aliasing filter therefore usually precedes the ADC.

Quantization rounds the sampled voltage to the nearest of 2^N representable codes (for N-bit resolution). The resulting unavoidable difference is the quantization error, which appears as quantization noise in the output signal. Key parameters for evaluating real converters are SNR (signal-to-noise ratio), SFDR (spurious-free dynamic range), and ENOB (effective number of bits) – the actually usable resolution accounting for noise and distortion.

The SAR ADC converts a sampled voltage into a digital code through a binary search. An internal register tests bit by bit, starting with the most significant bit (MSB), whether the corresponding code value lies above or below the input voltage, using an internal DAC to generate the comparison voltage and a comparator to make the decision.

For a resolution of N bits, the conversion requires exactly N comparison cycles – conversion speed therefore scales linearly with resolution. SAR ADCs feature small area, low power consumption, and moderate-to-high resolution (typically 8–18 bits) at medium sample rates (kHz to a few tens of MHz), making them today's most widely used ADC architecture in mixed-signal ICs.