Sequential Logic: Flip-Flops, Latches, and Clock Trees

The simplest bistable element can be built from two cross-coupled NOR or NAND gates and is called an SR latch (set-reset latch). In the NOR version, the circuit holds its state as long as both inputs S (set) and R (reset) are 0; a high level on S sets the output Q to 1, a high level on R resets it to 0, and the combination S=R=1 is defined as a forbidden state, since both outputs Q and the inverted Q̄ then fall to 0 simultaneously, leaving the subsequent state undefined once both inputs return to 0 together – which of the two gates "wins" depends on tiny propagation delay differences.

The feedback that gives the latch its name arises because the output of each gate is fed back to the input of the other: once a state is set, it holds itself, since both gates mutually "support" each other as long as S and R remain 0 – this same principle of positive feedback also underlies the latches and flip-flops discussed in the following sections. An equivalent NAND-based version, in which the inputs S̄ and R̄ are active-low, is equally common in practice, for example for debouncing mechanical switches, where a single button press should produce only one clean state change despite multiple contact bounces.

The SR latch is therefore the simplest element capable of storing a single bit of state without requiring a clock signal – it responds immediately (asynchronously) to changes on S and R, which also makes it susceptible to brief glitches. Adding a clock signal and a gating circuit that only lets S and R through during an active clock phase turns it into a clocked SR latch – the precursor to the edge-triggered flip-flops discussed in the following sections.

Building on the SR principle, four basic flip-flop types have become established in digital logic, differing in their input wiring and therefore in their behavior, even though internally they are ultimately all built from the same bistable element. The SR flip-flop inherits the behavior of the SR latch, including the forbidden state, only edge-triggered rather than level-sensitive. The JK flip-flop closes this gap: the combination J=K=1 is not forbidden but instead toggles the output on every active clock edge (Q switches to its complement); for J=1, K=0 it sets like the S input, for J=0, K=1 it resets like the R input, and for J=K=0 it holds its state.

The T (toggle) flip-flop is a special case of the JK flip-flop with a single input T that toggles on every clock cycle when T=1 and holds its state when T=0 – a function especially needed in frequency dividers and asynchronous counter circuits, since a chain of T flip-flops with T=1 at each output successively halves the clock frequency. Historically, SR, JK, and T flip-flops were built directly from discrete gates, before a more unified approach took hold with the spread of dense integrated circuits.

The D flip-flop (data or delay flip-flop), by far the most widely used in modern CMOS logic, simply captures the value present at the D input on every active clock edge, without the ambiguity of the SR flip-flop or the switching logic of the JK flip-flop – its characteristic equation is simply Q(t+1) = D. Because SR, JK, and T behavior can, if needed, also be reproduced with additional combinational logic in front of a D flip-flop (for example T = D XOR Q for toggle behavior), modern standard-cell libraries provide essentially only the D flip-flop as a base cell, and the following sections accordingly focus on its structure and timing behavior.