Semiconductor Technology from A to Z

A latch is a level-sensitive storage element: as long as the clock or enable signal is active, the output directly follows the input (transparent state); once the clock signal switches to the inactive level, the last applied value is frozen. A simple D-latch can be built from two cross-coupled inverters whose feedback path is opened and closed through a transmission gate; in modern standard-cell libraries, such a latch typically requires 6 to 8 transistors.

A flip-flop, by contrast, is edge-triggered: the stored value changes only at the moment of the rising or falling clock edge. The most common CMOS flip-flop is the master-slave flip-flop, in which two latches clocked in opposite phase are connected in series – the master latch tracks the input while the clock is low, and the slave latch captures the value of the master latch on the rising edge and holds it for the remainder of the clock period. Because of this cascading, at most one of the two latches is ever transparent at a given time, which prevents the input from passing directly to the output within a single clock period. Such a master-slave flip-flop typically consists of around 20 to 24 transistors; modern processor dies contain several hundred million to over a billion such flip-flops.

In a synchronous circuit, every flip-flop must receive a common clock signal that arrives at tens of thousands to millions of gates at nearly the same time. Since a single clock source cannot drive the parasitic capacitance of all connected flip-flops, the clock is distributed through a clock tree: a hierarchy of typically 5 to 8 buffer stages that amplify the signal in stages while fanning it out to an increasing number of endpoints.

The timing difference with which the clock arrives at different flip-flops is called clock skew and arises from unequal wire lengths and buffer chains; in well-optimized designs, skew is usually kept to within 2 to 5 % of the clock period. In a symmetric clock tree such as an H-tree, the wire length from the root to every endpoint is deliberately kept identical to minimize skew. Because clock wiring and its buffers alone can account for 20 to 30 % of a digital chip total dynamic power, optimizing the clock tree (clock tree synthesis) is one of the most demanding steps in digital backend design.

In addition to the clocked data input, most flip-flops have separate, asynchronously acting control inputs for setting or resetting the stored value. These act immediately, independent of the clock edge, and are used, for example, to force a defined initial state when the circuit is powered on.

For manufacturing test, regular flip-flops are frequently replaced with scan flip-flops, which have an additional data input and a selection multiplexer and typically require only about 5 to 10 % more area than a regular flip-flop. In test mode, all scan flip-flops on a chip are connected into one or more long shift-register chains, often with several thousand elements per chain, through which arbitrary test patterns can be shifted in and the resulting states shifted back out. This approach, known as design for test (DFT), typically achieves fault coverage above 98 % in modern designs and makes logic states deep inside a chip observable and controllable from the outside without requiring additional test pins.