Semiconductor Technology from A to Z

In 2.5D integration, several fully processed dies are not stacked directly on top of one another but placed side by side on a shared carrier substrate -- the interposer. The interposer itself contains no active transistors; it serves purely as a high-density wiring layer that connects the individual dies to one another and to the package substrate beneath.

The name "2.5D" reflects that an additional vertical layer is added -- the dies sit on the interposer, which in turn connects to the package via TSVs -- while the actual chip integration still happens laterally (side by side), in contrast to the true, vertically stacked 3D stacking covered in the following chapter. This lateral arrangement considerably simplifies heat dissipation compared to stacked dies, since each chip retains direct thermal contact with the cooling solution above it.

• Silicon interposer: manufactured from a silicon wafer, penetrated by TSVs for through-connections and several metallization layers (RDL, see below) on top. Silicon allows very fine wiring structures (sub-micrometer pitch), since it can be processed with the same lithography and etching techniques as a regular logic wafer. However, it is comparatively expensive to produce and limited in area (typically to the size of a lithography reticle, i.e. a few centimeters per side), which requires additional stitching techniques to join multiple reticle fields for very large systems.
• Organic interposer: based on printed-circuit-board-like materials, significantly cheaper and producible in larger areas -- dimensions well beyond the reticle limit are readily achievable here. However, it only achieves coarser wiring densities, since the manufacturing techniques used (drilling, electroplated through-holes) do not approach the precision of semiconductor lithography.

The choice between the two variants is therefore essentially a trade-off between interconnect density and cost/area, which plays out differently depending on the application.

The redistribution layer is an additional metallization layer on the interposer (or directly on a die) that "redistributes" a chip's comparatively coarse contact pads onto the much finer connection structures of the interposer -- hence the name. Without an RDL, the chip's fine, densely packed connections would have to meet the coarser interposer or package structures directly, which would be mechanically and electrically problematic.

RDL structures are manufactured with lithography and copper technologies similar to the BEOL wiring of a regular chip, but with coarser feature widths and significantly thicker traces, since current-carrying capacity matters more here than maximum density -- RDL traces often need to carry substantial supply currents, not just fast but low-current logic signals.

The most prominent application example is the pairing of a logic die (e.g. a GPU) with several high-bandwidth-memory stacks on a shared silicon interposer. The extremely short, dense connection paths across the interposer enable memory bandwidths that classical PCB wiring could not achieve -- while a DRAM module on a PCB routes only a handful of signal lines with limited clock frequency to the processor, the thousands of fine interposer connections allow massively parallel, wide data exchange at comparatively low clock frequency per line -- a concept that improves energy efficiency and bandwidth simultaneously (see HBM as a Flagship Example).

Interposer with logic die and HBM stack