Semiconductor Technology from A to Z

The basic structure and operating principle of this device are covered in the Fundamentals chapter Transistors and Memory. The following sections describe fabrication in detail.

1. Substrate

As with any silicon transistor, the basis for a FinFET is a lightly p-doped silicon substrate.

2. Hard Mask

A hard mask is deposited on the substrate, usually a stack of oxide and silicon nitride. It later transfers the lithographic pattern into the silicon with markedly less loss than a resist-only process.

3. Fin Lithography

Photoresist is patterned into narrow strips that set the position and width of the later fins. In the first volume-production processes, the fin width was 10 to 15 nm and has since dropped to just a few nanometers; the height should ideally be twice that or more. Such narrow fins can no longer be exposed directly; they are instead created through multipatterning: the fin width results from the thickness of a deposited layer, not from a mask.

4. Fin Etch

In a highly anisotropic dry etch step, the free-standing fins are etched into the silicon substrate. In the bulk process, the etch has to be time-based, since unlike with an SOI substrate there is no stop layer within the silicon to indicate the depth reached.

5. Removing the Hard Mask

Resist and hard mask are removed. The bare etched fins stand ready for isolation.

6. STI Oxide

For isolation, a Shallow Trench Isolation (STI) oxide is deposited that must provide good fill behavior for narrow, deep trenches – it completely overfills the trenches between the fins in the process.

7. STI Planarization

The oxide is planarized by chemical mechanical polishing. The hard mask serves as the stop layer.

8. STI Recess

In a further, time-based etch step, the oxide is selectively etched back until the fins protrude from the oxide at the desired height – the three-dimensional structure characteristic of the FinFET emerges. What remains is a lateral isolation between the fins. Since the fins are still connected to one another through the substrate, a doping step is required to electrically isolate the silicon fins from each other (not shown). Alternatively, the oxide can be grown into the base region of the fins in a high-temperature step, isolating the channels from the silicon substrate. In volume production, the first approach has prevailed: a region beneath the fin is deliberately heavily doped so that no conductive path can form there.

9. Gate Dielectric

The gate dielectric is formed on the exposed fin flanks to isolate the channel region from the gate electrode. In volume production, this is no longer a thermally grown oxide, but a layer of hafnium dioxide deposited by atomic layer deposition on top of a thin interfacial layer of silicon dioxide. Only atomic layer deposition coats a tall, narrow fin evenly on all three exposed sides.

10. Dummy Gate

The actual gate material used later is a metal, whose work function is chosen so as to yield the desired threshold voltage – a different metal for n-channel and p-channel transistors, respectively. Because this metal would not survive the later high-temperature steps, it is introduced only at the very end. First, a placeholder gate of polysilicon is used, deposited here conformally so that it already wraps around the fins completely. All the high-temperature process steps are carried out with this placeholder, which is removed again afterward (step 18). This approach is called the gate-last, or replacement-gate, process.

11. Gate Lithography

A resist strip running across the fins, together with a hard mask, defines the position and length of the gate – perpendicular to the cross-section shown here.

12. Dummy Gate Etch

Excess polysilicon is removed by reactive ion etching. What remains is the dummy gate stack, which still wraps around the fins on three sides.

13. Spacer

A nitride spacer is deposited conformally and etched back anisotropically, remaining as a sidewall spacer on the gate flanks. It protects the flanks during the following steps and later sets the distance between the gate and the source/drain contacts. A similar nitride layer between the fin and the gate can also be used deliberately to suppress the influence of the top gate segment on the channel, if only lateral control from the sides is desired.

14. Source/Drain Recess

Outside the gate – in the cross-section through the later source/drain region – the fin is deliberately recessed to make room for the subsequent epitaxy. Source and drain sit along the same fin: one before and one behind the gate, along the direction of current flow. Each individual fin therefore forms a complete channel on its own, with its own source and drain region at its two ends – with several parallel fins under a shared gate, every single fin contributes to both source and drain, rather than one fin belonging to source and another to drain.

15. Source/Drain Epitaxy

Selective epitaxy grows doped silicon (for nFETs typically Si:P, for pFETs SiGe:B) in a diamond shape on the fin stub. This characteristic "raised source/drain" geometry further increases the effective channel cross-section and lowers the access resistance. For p-channel transistors, a further effect comes into play: SiGe has a larger lattice constant than silicon and is laterally compressed as it grows epitaxially on the fin, matching the fin's crystal lattice. The resulting compressive strain is transmitted directly into the adjacent channel, where it acts uniaxially along the current direction and specifically increases hole mobility, and with it the drive current.

16. Interlayer Dielectric

The interlayer dielectric (ILD) is deposited over the whole wafer and initially covers the dummy gate stack completely as well.

17. CMP

Chemical mechanical polishing removes the excess interlayer dielectric until the top of the dummy gate is exposed.

18. Removing the Dummy Gate

The polysilicon of the placeholder gate is selectively etched out – the spacer forms the walls of the open gate trench, ready for the actual metal gate.

19. High-k/Metal Gate

Work-function metal and fill metal are deposited conformally into the trench. Because the metal layers to the left and right of the channel and above it can in principle differ, this can, if needed, produce several separately tunable gate electrodes for a single transistor. The final gate wraps around the channel on three sides.

20. Gate CMP

A final polishing step removes excess gate metal and electrically separates neighboring gates.

Which of a fin's two source/drain regions actually acts as source and which as drain is not a fixed property of the structure, but depends on the applied potential: for an n-channel transistor, the region at the lower potential takes on the role of the source, the one at the higher potential that of the drain (the reverse for p-channel transistors) – in every case, the channel is switched into conduction exclusively by the gate above it. This is why several gates can be placed independently along the same fin, as shown in the figure below: each gate controls only the channel segment directly beneath itself, regardless of whether a neighboring gate happens to be conducting or blocking at that moment. The shared source/drain region between two gates is, electrically, simply a node that acts as the drain of one transistor and the source of the other, depending on the switching state.

21. Contacts

Contact holes are etched down to the gate as well as source and drain and filled with metal – the FinFET is ready for electrical connection. The source/drain contacts lie outside the cross-sectional plane shown here.

Since, in an SOI-based process, a full-area oxide layer is already present on the wafer, the electrical isolation of the channels from one another is automatically ensured, without the additional doping step described in step 8. In addition, the fin etch process is less problematic, since it can simply be stopped on the buried oxide instead of having to rely on a time-based etch.

The evolution from the planar transistor through the FinFET to the nanosheet follows a single idea: the gate should enclose the channel from as many sides as possible. The more completely it surrounds it, the more reliably the transistor switches off – and the shorter the channel can be made without current flowing through it uncontrolled.

Gate enclosure compared

Why the fin reached its limit

The FinFET solved the problem of the planar transistor, but brought two problems of its own.

First, a fin that has to become ever narrower while also growing taller becomes mechanically unstable. It stands freely on the substrate and has to survive several process steps without toppling over or breaking.

Second, the gate width can now only be adjusted in discrete jumps. In the planar transistor it was a freely chosen quantity in the design; in the FinFET it results from the number of fins. A transistor can therefore have two or three fins, but nothing in between. Anyone needing a somewhat stronger driver immediately gets a substantially stronger one – along with the corresponding area and power consumption.

Laying the fin down

The successor rotates the fin by 90 degrees: instead of a single vertical fin, several horizontal silicon layers are stacked on top of one another, each fully enclosed by the gate. Because the gate now surrounds the channel on all sides, it is called a gate-all-around transistor; based on the shape of the layers, it is also called a nanosheet transistor.

Both disadvantages of the fin disappear as a result. The layers are held by the gate and are not free-standing. And the gate width is once again continuously adjustable, since it results from the width of the layers – which can be freely chosen in the design, rather than counted out in fins.

How the layers are formed

The decisive trick lies in the fabrication. A stack of alternating silicon and silicon-germanium layers is grown epitaxially on the substrate. A fin is first etched out of this stack, just as with the FinFET. The silicon-germanium is then removed selectively – it dissolves in a chemistry that leaves the silicon untouched. What remains are the free-floating silicon layers, whose gaps are then filled with dielectric and gate metal.

The thickness of the layers and their spacing are therefore not determined by lithography, but by the layer thicknesses used during growth. The gap between two layers is only a few nanometers wide, and dielectric and metal have to reach completely into this gap – a task that cannot be accomplished without atomic layer deposition.

What comes next

The next step is already emerging and takes the idea to its logical conclusion: instead of placing n-channel and p-channel transistors side by side, they are meant to be stacked on top of one another. The resulting complementary FET saves area, since both transistors occupy the same footprint. The effort required is considerable, since two differently doped devices have to be built within a single, shared process flow.