1. Fundamentals
The basic structure and operating principle of this device are covered in the Fundamentals chapter Transistors and Memory. The following sections describe fabrication in detail.
2. Fabrication of an n-Channel FET
1. Substrate
The basis for an n-channel field-effect transistor is a p-doped silicon substrate, using boron as the dopant.
2. Oxidation
Silicon dioxide SiO2 (the gate oxide, GOX for short) is grown on the substrate by dry oxidation. It insulates the gate, deposited later, from the substrate.
3. Deposition
Nitride is deposited in an LPCVD process; it later serves as a mask during field oxidation.
4. Photolithography
A photoresist is applied on top of the nitride, exposed, and developed, producing a structured resist layer that serves as an etch mask.
5. Etching
The resist masks the nitride; the exposed areas are removed by reactive ion etching.
6. Resist Removal
After the pattern has been transferred into the nitride, the resist is removed wet-chemically using a developer solution.
7. Oxidation
The nitride acts as a mask; thermal wet oxidation occurs only where the nitride has been removed. The field oxide (FOX, e.g. 700 nm) provides lateral isolation from neighbouring devices.
8. Etching
After oxidation, the nitride is removed in a wet-chemical etching process.
9. Deposition
Polycrystalline silicon is deposited in an LPCVD process.
10. Photolithography
A resist layer is patterned on top of the polysilicon to serve as an etch mask.
11. Etching
The photoresist again acts as an etch mask, and the silicon is patterned in a reactive ion etch step, forming the gate electrode that controls the transistor.
12. Resist Removal
After etching, the resist is again removed wet-chemically.
13. Oxidation
A thin oxide, the post-oxide, is deposited next. It protects the gate electrode and also acts as a spacer for the source/drain implantation.
14. Ion Implantation
In an implantation step using phosphorus ions, the source and drain regions are n-doped. Since the gate electrode acts as an implantation mask, defining the width of the n-channel between source and drain, this is referred to as self-alignment. By adjusting the width of the spacers, the distance between the implanted dopant atoms and the gate can be precisely controlled according to the electrical requirements.
15. Oxidation
An oxide (the interlayer oxide, ILD for short, e.g. 700 nm) is deposited to insulate against the metallization layers above. This is done in an LPCVD process using TEOS, which provides good step coverage.
16. Photolithography and Etching
A further resist layer is patterned, and the edges of the contact holes are rounded off in an isotropic etch process.
17. Etching
The contact holes are then opened down to the n-doped regions and to the gate in an anisotropic etch process.
18. Metallization
The contact holes are filled with aluminium in a sputtering process.
19. Photolithography
In a final lithography step, another resist layer is patterned.
20. Etching
The resist pattern is transferred into the underlying metallization layer in an anisotropic dry etch step.
21. Resist Removal
Finally, the resist is removed, leaving behind aluminium interconnects that drive the transistor.
The actual structure of a transistor is considerably more complex. Additional planarization layers may be used to support the lithographic processes, and several drain/source implantations may be carried out to precisely set the threshold voltage. Additional spacers at the gate are likewise possible, in order to fine-tune the channel length or influence the doping profile.