Semiconductor Technology from A to Z

A MOSFET can be reduced to its simplest function: a voltage-controlled switch. Current either flows between source and drain or it doesn't, depending on the voltage applied to the gate. This makes it fundamentally different from a mechanical switch — nothing moves, there's no wear, and switching takes only a fraction of a nanosecond.

In an enhancement-mode NMOS transistor, no conducting channel exists between source and drain without gate voltage. Only once the gate voltage exceeds the threshold voltage does the channel form, and the transistor conducts. Think of the gate as a switch's control input: 0 V at the gate → switch open; enough positive voltage at the gate → switch closed.

Alongside the NMOS transistor there's its counterpart, the PMOS transistor. It behaves as a mirror image: while the NMOS conducts at a high gate level, the PMOS blocks at exactly that point — and instead conducts at a low level. This complementarity isn't a footnote; it's the core principle behind all of CMOS technology ("Complementary MOS").

The NMOS is typically used as the connection to ground (0 V), the PMOS as the connection to the supply voltage. This interplay lets both transistor types together switch an output cleanly between High and Low, without ever creating a direct short between supply and ground.

Wiring a PMOS and an NMOS together as follows creates the simplest of all logic gates: the inverter (NOT gate).

• The PMOS sits between the supply voltage (VDD) and the output.
• The NMOS sits between the output and ground (GND).
• Both gates are tied together and form the input.

Apply Low (0 V) at the input, and the NMOS blocks while the PMOS conducts — the output is connected to VDD through the PMOS and sits at High. Apply High, and the picture flips: the PMOS blocks, the NMOS conducts, the output is pulled to ground and sits at Low. The output is thus always the opposite of the input — hence the name inverter.

Notably, in neither stable state does current flow from VDD to GND, since exactly one of the two transistors is always blocking. That's why CMOS circuits draw very little power at rest.

This means the two transistors in the inverter also take on the classic roles of pull-up and pull-down: the PMOS actively pulls the output to VDD (pull-up), the NMOS actively pulls it to GND (pull-down). Since the two are never active at once, there's never a short circuit — and the output always has a clearly defined level in every state, instead of floating.

A handful of transistors is all it takes to build a first composite gate. The principle: two NMOS transistors are wired in series between the output and ground. Only when both inputs are High do both transistors conduct, clearing the path to ground — pulling the output Low. If even one input is Low, the series path is broken.

In parallel, two PMOS transistors sit between the output and the supply voltage. If both inputs are High, both PMOS block, and neither pulls the output up. If at least one input is Low, the corresponding PMOS conducts and pulls the output High.

The output is therefore Low only when both inputs are High — otherwise High. That is the definition of NAND. NAND is therefore not a derived gate but the original one: it arises directly from series and parallel transistor arrangements, with no detour and no extra inverter at the output.

This is precisely why NAND holds special significance in CMOS technology: it needs only the minimum of four transistors, and wired to itself it can be composed into any other gate — NAND is considered a "universal" gate.

NOR is the mirror image of NAND: two parallel NMOS transistors as pull-down, two series PMOS transistors as pull-up. As soon as at least one input is High, the corresponding NMOS conducts and pulls the output Low. Only when both inputs are Low do both NMOS block at once while both PMOS conduct — only then does the output get pulled High through the complete series path.

NOR, too, is thus a "native" CMOS gate with a minimal transistor count of four, and like NAND it is universal: any logic function can be built from NOR gates alone. Adding an inverter at the output later turns it into the OR gate.

The AND gate builds directly on the NAND gate introduced above: take exactly the same circuit of two parallel PMOS and two series NMOS transistors, and add an inverter at the output. Where NAND pulls the output Low for two High inputs, the inverter turns that back into High — the output is now High exactly when both inputs are High.

This extra inverter stage is why AND always needs two more transistors than the underlying NAND gate in CMOS — an inverter consists of one PMOS and one NMOS, so four transistors become six. AND is a derived gate, NAND the "natural" building block of the technology.

Just as AND builds on NAND, OR arises from the NOR gate introduced above: the same circuit of two parallel NMOS and two series PMOS transistors, with an inverter added at the output. Where NOR pulls the output Low for at least one High input, the inverter turns that back into High — the output is now High exactly when at least one input is High.

As with the AND gate, this extra inverter costs two more transistors than the underlying NOR gate — a small but consistent trend when moving from the native CMOS building blocks to AND and OR.

XOR can no longer be realized with a simple series or parallel arrangement of just two transistors each — the function “output High when the inputs differ” needs more degrees of freedom. A compact solution common in practice uses transmission gates: input A and its inverted counterpart, obtained through an extra inverter, produce two complementary control signals.

One transmission gate passes input B through to the output unchanged when A is High. A second transmission gate passes the inverted B through when A is Low. At the shared output node, depending on the state of A, either B or its inverse appears — exactly the XOR function.

Altogether, this implementation needs six transistors: two for the inverter on A, and two each — one NMOS and one PMOS — for the two transmission gates. That makes XOR more involved than the other five gates, which shows up in practice as higher area and power requirements.

All the common logic gates can be derived from the basic circuits covered so far. The table below shows the gate symbol and truth table for the most important gates: