Semiconductor Technology from A to Z

A MOSFET can be reduced to its simplest function: a voltage-controlled switch. Current either flows between source and drain or it doesn't, depending on the voltage applied to the gate. This makes it fundamentally different from a mechanical switch — nothing moves, there's no wear, and switching takes only a fraction of a nanosecond.

In an enhancement-mode NMOS transistor, no conducting channel exists between source and drain without gate voltage. Only once the gate voltage exceeds the threshold voltage does the channel form, and the transistor conducts. Think of the gate as a switch's control input: 0 V at the gate → switch open; enough positive voltage at the gate → switch closed.

Alongside the NMOS transistor there's its counterpart, the PMOS transistor. It behaves as a mirror image: while the NMOS conducts at a high gate level, the PMOS blocks at exactly that point — and instead conducts at a low level. This complementarity isn't a footnote; it's the core principle behind all of CMOS technology ("Complementary MOS").

The NMOS is typically used as the connection to ground (0 V), the PMOS as the connection to the supply voltage. This interplay lets both transistor types together switch an output cleanly between High and Low, without ever creating a direct short between supply and ground.

Wiring a PMOS and an NMOS together as follows creates the simplest of all logic gates: the inverter (NOT gate).

• The PMOS sits between the supply voltage (VDD) and the output.
• The NMOS sits between the output and ground (GND).
• Both gates are tied together and form the input.

Apply Low (0 V) at the input, and the NMOS blocks while the PMOS conducts — the output is connected to VDD through the PMOS and sits at High. Apply High, and the picture flips: the PMOS blocks, the NMOS conducts, the output is pulled to ground and sits at Low. The output is thus always the opposite of the input — hence the name inverter.

Notably, in neither stable state does current flow from VDD to GND, since exactly one of the two transistors is always blocking. That's why CMOS circuits draw very little power at rest.

This means the two transistors in the inverter also take on the classic roles of pull-up and pull-down: the PMOS actively pulls the output to VDD (pull-up), the NMOS actively pulls it to GND (pull-down). Since the two are never active at once, there's never a short circuit — and the output always has a clearly defined level in every state, instead of floating.

A handful of switches is all it takes to build an AND function from two individual switches. The principle: two NMOS transistors are wired in series between the output and ground. Only when both inputs are High do both transistors conduct, clearing the path to ground — pulling the output Low. If even one input is Low, the series path is broken.

In parallel, two PMOS transistors sit between the output and the supply voltage. If both inputs are High, both PMOS block, and neither pulls the output up. If at least one input is Low, the corresponding PMOS conducts and pulls the output High.

This circuit is, at first, a NAND gate (output Low only when both inputs are High — the inverse of AND). Only a following inverter (see "The Inverter") turns it into a true AND gate. That's no coincidence: in CMOS technology, NAND and NOR gates are the "natural" building blocks, since they arise directly from series and parallel arrangements of transistors — AND and OR only appear once an extra inverter is added at the output.

All the common logic gates can be derived from the basic circuits covered so far. Two symbol standards have become established for the graphical representation: the older ANSI/MIL-STD-806 symbols (common in the US, with distinctive curved shapes) and the IEC 60617 symbols (common in Europe, rectangles labeled &, ≥1, 1). The table below shows the gate symbol and truth table for the most important gates: