Fabrication of Optoelectronic Devices

The fabrication of optoelectronic devices begins with epitaxial crystal growth – unlike many electronic devices, simply doping the substrate isn't sufficient here, since the active region consists of several precisely controlled heterolayers (barriers, quantum wells, DBR stacks) whose thickness and composition directly determine the emission wavelength. Even the smallest crystal defects – dislocations, point defects, impurities – act as non-radiative recombination centers and measurably reduce quantum efficiency. While a MOSFET still tolerates defect densities in the range of 10⁴–10⁵ cm⁻², the same defect densities in an LED active region already cause noticeable efficiency losses; commercial GaN LEDs require dislocation densities well below 10⁸–10⁹ cm⁻², ideally lower still.

MOCVD (Metal-Organic Chemical Vapor Deposition, also called MOVPE) is the industry standard for mass production. Metal-organic precursors – such as trimethylgallium (TMGa), trimethylindium (TMIn), trimethylaluminum (TMAl) – and hydrides (ammonia NH₃ for nitride compounds, arsine AsH₃ or phosphine PH₃ for arsenides/phosphides) are carried in a gas stream (usually hydrogen or nitrogen) over the substrate, heated to 600–1100 °C, where they decompose thermally (pyrolysis), and the released atoms incorporate at the growth front. The process runs at atmospheric or moderate reduced pressure, allows high throughput across multiple wafers simultaneously in planetary reactors, and therefore dominates commercial LED and laser fabrication almost entirely.

MBE (Molecular Beam Epitaxy), by contrast, operates in ultra-high vacuum (below 10⁻¹⁰ mbar) with molecular beams from effusion-cell-evaporated elements that condense directly on the substrate without a chemical reaction. The growth rate, typically around one monolayer per second, is markedly lower than MOCVD rates, but layer thickness can be controlled down to the monolayer and monitored in situ via RHEED (Reflection High-Energy Electron Diffraction) – the diffraction pattern shows in real time whether the surface is growing atomically smooth. Due to the lower throughput and higher equipment cost, MBE remains largely reserved for research and specialty applications with particularly demanding heterostructures, such as VCSEL DBR stacks with extremely sharp interfaces.

A central challenge in both processes is lattice matching: growing a material with a differing lattice constant on a substrate creates strain that relaxes through dislocation formation above a critical layer thickness (often just a few nanometers for strong mismatch) – with a directly measurable effect on the resulting device efficiency. GaN, for instance, is usually grown on sapphire (Al₂O₃) or SiC due to the lack of economically available bulk GaN substrates, despite a substantial lattice mismatch of up to 16% for GaN-on-sapphire. A thin AlN or GaN nucleation layer grown at low temperature (500–600 °C) serves as a buffer layer: it initially grows amorphous to polycrystalline, is then annealed and recrystallizes, relieving part of the strain before the actual single-crystal GaN growth continues at 1000–1100 °C.

After epitaxial growth, a continuous layer structure initially covers the entire wafer – for individually addressable devices, it must be divided into isolated mesa structures. Dry etching processes, for III-V materials usually ICP-RIE (Inductively Coupled Plasma Reactive Ion Etching) with chlorine-based chemistry (Cl₂/BCl₃ mixtures, since fluorine chemistry doesn't form sufficiently volatile etch products with Ga and In compounds), remove the layers down below the active region. Etch depth is typically a few micrometers and defines both the lateral extent of each individual device and the electrical isolation of neighboring structures on the same chip – insufficient isolation would cause parasitic leakage currents between neighboring LEDs or lasers on the same wafer.

Contact metallization follows, with fundamentally different requirements on the p- and n-sides. The p-side typically uses Ti/Au or Ni/Au layer stacks, often supplemented with a thin Pt or Pd interlayer as a diffusion barrier; they must achieve as low a specific contact resistance as possible (in the range of 10⁻⁵–10⁻⁶ Ω·cm²) while also providing good current spreading, which is technologically more demanding than n-contacts due to the lower hole mobility in p-type semiconductors. LEDs therefore often add a transparent, conductive ITO layer (indium tin oxide, sheet resistance typically 10–30 Ω/sq) between the metal contact and p-GaN, to distribute current evenly across the entire chip area without blocking light extraction with large-area, opaque metallization – ITO is over 90% transparent in the visible spectrum. The n-side typically gets a simpler Ti/Al-based contact with lower contact resistance, since n-type semiconductors inherently have lower contact barriers than p-type ones, owing to higher electron mobility and lower effective mass.

A distinctive feature of VCSEL fabrication is the oxide aperture, which solves one of the central problems of the vertical resonator concept: the need to concentrate the injection current onto the small active area. During epitaxy, a thin, AlAs-rich layer (typically over 98% Al content) is deliberately incorporated into the layer structure near the active region. After mesa etching, this layer is converted to insulating aluminum oxide (AlₓOy) through selective, lateral wet oxidation at elevated temperature in a humid nitrogen atmosphere, starting from the exposed mesa edges – the oxidation front grows from outside in at a material- and temperature-dependent, well-controllable lateral rate, so that only a small central opening a few micrometers in diameter remains unoxidized and thus conductive. This aperture forces the current into a narrowly confined central region of the active area and simultaneously acts as an optical waveguide (due to the oxide's lower refractive index) – both necessary to achieve the current density and transverse mode control needed for lasing despite the VCSEL's short gain length and small device area.

The VCSEL mesa's characteristic round shape comes from nothing more than the geometry of the photoresist mask used in the same ICP-RIE etch step: instead of the long, narrow stripe mask of an edge emitter, the photoresist is exposed and developed through a mask with circular openings (typically 15–30 µm in diameter), leaving round resist islands over the future mesas. The subsequent dry etch removes the unmasked material, leaving a cylindrical mesa pillar with a rotationally symmetric sidewall – this symmetry is exactly what allows the later lateral wet oxidation to grow radially inward evenly from all sides, forming a centered, circular aperture.