Semiconductor Technology from A to Z

The SiC power MOSFET adopts the planar DMOS base structure of its silicon counterpart (see the fundamentals chapter "The MOSFET"), but exploits the much higher breakdown field strength of SiC to make the drift region significantly thinner and more highly doped at the same blocking voltage. Concretely: while a 1200 V Si device needs a drift region several tens of micrometers thick with comparatively low doping, an equivalent SiC device gets by with a drift region only a few micrometers thick and considerably more highly doped.

This lowers the specific on-resistance R_on·A by more than an order of magnitude compared to an equivalent Si MOSFET – while simultaneously allowing a higher blocking voltage (600 V to over 3.3 kV) and a noticeably smaller chip area per ampere. In practice, however, the drift region alone does not limit the total resistance: channel resistance at the SiC/SiO2 interface (see the last paragraph of this chapter) and the JFET resistance between the p-wells contribute a substantial, sometimes dominant, share of the total resistance in modern planar SiC MOSFETs – a circumstance that has significantly driven the development of alternative cell concepts such as the trench MOSFET (see below). Commercial SiC MOSFETs today cover the range from 650 V to over 3.3 kV and have replaced the Si IGBT as the standard switching device in many applications.

A Si pn diode needs time when switching off to clear the minority charge stored during conduction – the so-called reverse recovery time, which causes switching losses that become more significant at higher frequencies. Physically, this is because a bipolar pn junction injects minority carriers into the adjacent region during conduction; when blocking, these must first be removed through recombination or sweep-out before the diode actually blocks – during which a non-negligible reverse current briefly flows.

A SiC Schottky diode, by contrast, is a pure majority-carrier device: there is virtually no stored charge and therefore almost no reverse recovery current, since the metal-semiconductor junction operates without minority carrier injection. This only becomes practical with SiC, because its high breakdown field strength allows Schottky contacts to sustain high blocking voltages with acceptable conduction losses – with silicon, Schottky diodes are only practical up to a few hundred volts, since the drift region would need to become so thick at higher voltages that the on-resistance would become unacceptably high. SiC Schottky diodes are now manufactured as standard in the 600 V to 1700 V range and are typically used as freewheeling diodes in combination with SiC or even Si MOSFETs, where their virtually loss-free switching behavior noticeably improves overall system efficiency.

In the planar SiC MOSFET, the channel lies horizontally at the wafer surface, similar to the Si DMOS. This design is the easiest to control from a manufacturing standpoint and was therefore the first commercially successful SiC MOSFET architecture; however, as noted in the previous paragraph, it suffers from the so-called JFET resistance – the constriction of current flow between two neighboring p-wells, which is especially pronounced in SiC due to the deep p-well implantation required.

Trench SiC MOSFETs instead place the channel along the vertical wall of an etched trench. This entirely avoids the JFET resistance of the planar structure (the constriction between two neighboring p-wells) and increases channel density, since the lateral JFET region can be dispensed with and cells can be packed more densely – at the cost of more complex fabrication and higher demands on field shielding at the trench bottom, where locally elevated electric fields would otherwise threaten gate oxide reliability. The electric field can concentrate especially strongly at the trench corners, which is why practical trench designs include additional deep p-implants at the trench bottom that act as a field shield and protect the gate oxide from field peaks. Leading manufacturers are increasingly adopting trench architectures, since they achieve a noticeably lower on-resistance than planar cells at the same chip area.

Unlike with silicon, thermal oxidation of SiC leaves part of the carbon behind as interface defects, since during oxidation the silicon reacts with oxygen to form SiO2, but the released carbon is not fully removed as CO or CO2 and instead partly remains as carbon clusters and interface states near the conduction band. This elevated defect density at the SiC/SiO2 interface reduces the effective channel electron mobility to a fraction of the bulk value – often just a few percent of the theoretically possible mobility in bulk SiC.

This is a key reason why SiC MOSFETs long lagged behind their theoretical potential despite superior material properties: the Baliga figure of merit predicts a very low on-resistance, but the actually achievable channel mobility long limited real devices far more strongly than in silicon MOSFETs. Process improvements such as NO or N2O post-oxidation annealing (nitrogen passivation) have significantly improved interface quality and therefore channel mobility in recent years, since the incorporated nitrogen passivates part of the interface states and thereby reduces scattering of channel electrons. Current research is also exploring alternative crystal orientations (such as the a-plane instead of the usual Si-face) as well as new passivation chemistries, aiming to bring interface quality further toward the theoretical material limit.