Semiconductor Technology from A to Z

Unlike silicon, SiC cannot be pulled from a melt – at the temperatures required, SiC sublimes rather than melting, since no liquid phase exists at normal pressure (SiC decomposes directly into the vapor phase above about 2830 °C). A Czochralski or Bridgman process, as used for silicon, is therefore ruled out from the start. Instead, the PVT process (Physical Vapor Transport, also known as the modified Lely method) is used: a supply of SiC powder is heated above 2000 °C and sublimes, the vapor phase – consisting mainly of Si, Si2C and SiC2 – travels along a temperature gradient to a cooler SiC seed crystal and crystallizes there epitaxially.

The process runs for days to weeks and grows a cylindrical boule, from which wafers are subsequently sawn. Growth rates are typically only a few hundred micrometers per hour, which makes the process comparatively slow and cost-intensive – a key reason why SiC substrates remain more expensive than silicon substrates to this day. Precise control of the temperature gradient inside the closed graphite crucible is critical for ensuring uniform, low-defect crystallization across the entire boule diameter; deviations quickly lead to micropipes, dislocations, or parasitic polytype inclusions. Sawing is followed by extensive lapping, polishing and CMP steps until an epitaxy-ready wafer surface with an atomically smooth terrace structure is achieved.

SiC occurs in more than 200 crystal structures (polytypes), which differ only in the stacking sequence of the Si-C double layers along the c-axis – this is known as polytypism, since materials with identical chemical composition end up with different electronic properties. The most common polytypes are 3C (cubic), 4H and 6H (both hexagonal), named after the number of Si-C double layers in the repeating stacking sequence.

4H-SiC has become the standard for power electronics because it offers higher and more isotropic electron mobility than, for example, 6H-SiC, whose mobility can vary by up to a factor of three depending on crystal direction. 4H-SiC also has a larger bandgap than 6H-SiC (3.26 eV versus 3.0 eV) and therefore a higher breakdown field strength, making it additionally attractive for high-voltage applications. Growth is usually performed off-axis (typically a 4° miscut from the c-axis, 8° in earlier processes) to force step-flow growth during homoepitaxy, in which atoms preferentially attach at existing step edges rather than nucleating new islands. Without this deliberate miscut, the thermodynamically more favorable 3C polytype would tend to form, leading to disruptive polytype inclusions and local crystal defects within the 4H lattice.

Native GaN substrates are expensive and available only in small diameters (usually 2 to 4 inches), because GaN does not melt congruently at normal pressure – a melt-based process as used for silicon or SiC is therefore not practical, and alternative approaches such as ammonothermal or HVPE growth of bulk crystals remain slow and expensive to this day. In practice, GaN is therefore deposited heteroepitaxially on foreign substrates – usually silicon (GaN-on-Si, low cost, large diameters up to 200 mm and thus compatible with existing Si production lines) or silicon carbide (GaN-on-SiC, better heat dissipation thanks to SiC's high thermal conductivity, but considerably more expensive and usually limited to smaller diameters).

A thin AlN nucleation layer along with step-graded AlGaN buffer layers absorb the lattice and thermal expansion mismatch before the actual GaN layer grows. The AlN nucleation layer initially serves chemical decoupling, since at the high growth temperatures silicon can undergo undesired reactions with the Ga precursor (meltback etching); the subsequent step-graded AlGaN buffer layers, with successively decreasing Al content, build up the compressive pre-stress that later counteracts the tensile stress arising from the thermal expansion mismatch on cooling. Only this carefully tuned layer design makes it possible to grow crack-free GaN layers several micrometers thick on silicon wafers, typically by MOCVD (Metal-Organic Chemical Vapor Deposition).

The lattice constants of GaN and silicon differ by about 17%, and their thermal expansion coefficients by more than 50% – without buffer layers, the GaN layer would crack on cooling from the growth temperature (typically above 1000 °C) to room temperature, since the thermal mismatch generates substantial tensile stress in the GaN film. The step-graded AlGaN buffer architecture described in the previous paragraph is specifically designed to build up a compressive counter-stress that compensates for this thermal tensile stress on cooling.

Even with a buffer strategy, a significant dislocation density remains (typically 10⁸–10⁹ cm⁻² for GaN-on-Si, versus 10³–10⁴ cm⁻² for native SiC substrates) – a difference of roughly five orders of magnitude that has direct consequences for leakage behavior, reliability under dynamic stress (dynamic on-resistance drift) and long-term device stability. These dislocations act as leakage paths and recombination centers, ultimately limiting how high a practically usable blocking voltage a GaN-on-Si device can reach before reliability issues arise. This explains the industry's trade-off: GaN-on-Si for cost- and area-driven applications in the roughly 650–900 V range, GaN-on-SiC or – for the highest demands – native SiC substrates, where reliability and thermal management take priority and higher substrate costs are accepted.