The CMOS Fabrication Flow

A finished chip is the result of often several hundred individual process steps, which can be roughly divided into two major phases: Front-End of Line (FEOL) and Back-End of Line (BEOL). The FEOL builds the actual transistors – from the well through the gate to the doping. The BEOL then wires these transistors together into a working circuit across several metal layers.

The individual detail chapters on this site – for example on FET fabrication or FinFET technology – each cover a section of this flow in great depth. This chapter serves a different purpose: it places the individual steps into the overall process and shows how FEOL and BEOL interlock.

Every CMOS fabrication process starts with the silicon wafer – a thin, highly pure disc of single-crystal silicon. The first step is forming the wells: regions with deliberately introduced n- or p-type doping, in which the complementary transistor types will later be built. PMOS transistors grow in an n-well, while NMOS transistors form in the surrounding p-doped substrate (or a p-well).

To keep neighboring transistors from interfering with each other, they are separated by Shallow Trench Isolation (STI): narrow, oxide-filled trenches that provide electrical isolation while also clearly defining the active areas in which the transistors will later be built.