Semiconductor Technology from A to Z

A finished chip is the result of often several hundred individual process steps, which can be roughly divided into two major phases: Front-End of Line (FEOL) and Back-End of Line (BEOL). The FEOL builds the actual transistors – from the well through the gate to the doping. The BEOL then wires these transistors together into a working circuit across several metal layers.

The individual detail chapters on this site – for example on FET fabrication or FinFET technology – each cover a section of this flow in great depth. This chapter serves a different purpose: it places the individual steps into the overall process and shows how FEOL and BEOL interlock.

Every CMOS fabrication process starts with the silicon wafer – a thin, highly pure disc of single-crystal silicon. The first step is forming the wells: regions with deliberately introduced n- or p-type doping, in which the complementary transistor types will later be built. PMOS transistors grow in an n-well, while NMOS transistors form in the surrounding p-doped substrate (or a p-well).

To keep neighboring transistors from interfering with each other, they are separated by Shallow Trench Isolation (STI): narrow, oxide-filled trenches that provide electrical isolation while also clearly defining the active areas in which the transistors will later be built.

On the prepared active areas, the actual transistor is then built: gate oxide, gate electrode, spacers, and the characteristic structure of source, drain, and channel. This flow is already described step by step in detail in the FET fabrication series and is not repeated here.

What matters for this overview is mainly the timing: every step up to and including gate patterning belongs to the FEOL. Only after that does the transition to the BEOL begin.

After gate patterning comes doping of source and drain – usually by ion implantation, in which dopant atoms are shot into the wafer at high energy. Spacers along the sides of the gate ensure that this implantation is offset precisely from the channel, creating a cleanly defined junction.

A thin metal layer (often nickel or cobalt) is then deposited on the exposed silicon surfaces – source, drain, and gate – and annealed. This forms a low-resistance metal silicide known as salicide (self-aligned silicide). It significantly reduces contact resistance and also marks the end of the FEOL.

With the transistor complete, the transition into the BEOL begins. First, an insulating layer (usually an oxide) is deposited over the entire structure and planarized. Tiny contact holes are then etched into this layer, landing precisely on source, drain, and gate, and are subsequently filled with tungsten.

These contacts form the first electrical connection between the transistor and the wiring layers above – the actual BEOL.

From here on, a pattern repeats across multiple layers: trenches and vias are etched into an oxide layer and then filled with copper using the so-called damascene process. Excess copper is removed again by chemical-mechanical polishing (CMP), leaving a flat surface for the next layer.

Modern processes use eight to fifteen metal layers this way – from very fine lower layers for local wiring to wide upper layers for power delivery. The process concludes with a passivation layer, which protects the chip from moisture and mechanical damage.

The following overview summarizes the entire flow from the well to the finished wiring once more and assigns the individual steps to the two main phases:

For a deeper look at individual steps, see the corresponding detail chapters: transistor fabrication in the FET series, the FinFET variant in the FinFET fabrication chapter, and layout and verification topics in the chapters on Design Rules and Layout versus Schematic.