Semiconductor Technology from A to Z

Everything about semiconductors and wafer fabrication

1. The Limits of Wet Etching

Anisotropic KOH/TMAH etching delivers precise geometries, but ones fixed by the crystal structure – on (100) silicon always the 54.74° angle, regardless of how narrow or deep the desired structure actually needs to be. For many MEMS applications, such as narrow, straight-walled trenches with a high aspect ratio (depth to width), this shape freedom is not sufficient.

DRIE (Deep Reactive Ion Etching) solves this problem with a dry, plasma-based process that can produce nearly arbitrary lateral geometries with nearly vertical walls – independent of the crystal orientation of the substrate.

2. The Bosch Process: Alternating Etch and Passivation

The dominant DRIE process today is the Bosch process, named after its inventor. It resolves the fundamental dilemma of reactive ion etchinghigh etch rate versus high anisotropy – by rapidly alternating two sub-steps. In the etch step, a fluorine-based plasma (usually SF₆) attacks the silicon isotropically, i.e. at roughly equal speed in all directions, for a few seconds. In the following passivation step, a different gas (usually C₄F₈, chemically related to Teflon) deposits a thin, polymer-like protective layer on all exposed surfaces, including the bottom of the trench just etched.

In the next etch step, directional ion bombardment strikes the passivation layer at the trench bottom more strongly than on the sidewalls and preferentially removes it there, so etching continues at the bottom while the sidewalls remain protected. This cycle of etching and passivating repeats hundreds to thousands of times, driving the trench deeper step by step.

3. Scallops: The Characteristic Wavy Structure

Because each etch step acts isotropically for a brief moment before the new passivation layer stops it, the sidewalls end up not perfectly smooth but slightly wavy, with characteristic horizontal ripples – the so-called scallops. Their size depends directly on the duration of the individual etch and passivation steps: shorter cycles produce finer scallops, longer cycles coarser ones, typically in the range of 50 to 500 nanometers.

For most MEMS applications, scallops are not a problem, but for optical applications (such as waveguides) or structures with particularly high surface-quality requirements, they can cause unwanted light scattering and require additional smoothing steps.

Cross-section of a DRIE-etched trench with scallop structure on the sidewalls, plus a magnified view of a single scallop

4. Aspect Ratio and Process Limitations

DRIE routinely achieves aspect ratios of 20:1 to 30:1, and significantly more in extreme cases – a narrow trench just a few micrometers wide can thus reach a hundred micrometers deep or more, with nearly vertical walls.

As depth increases, however, it becomes harder for both reactive species and ions to reach the bottom of the trench – an effect known as RIE lag: wider openings etch deeper faster than narrow ones, so structures of different widths on the same wafer end up at different depths after the same process time.