Semiconductor Technology from A to Z

The solar cell uses the same fundamental physical mechanism as the photodiode covered in Chapter 4 – absorption of a photon creates an electron-hole pair, separated by the electric field of a pn junction's depletion region – but pursues a fundamentally different goal. While the photodiode is optimized as a detector and typically operated in reverse bias to create a wide, high-field depletion region for high speed and sensitivity, the solar cell operates without external bias: it's meant to generate electrical power itself, not merely register a signal. Here the diode operates as a generator rather than a load – an operating regime referred to in the diode I-V plane as the fourth quadrant, where current and voltage have opposite signs relative to the usual diode convention.

Two limiting cases describe the illuminated cell's behavior. When the cell is short-circuited (terminal voltage U = 0), the short-circuit current I_sc flows – essentially the entire photogenerated current, since no opposing field prevents carriers from leaving the cell. When the cell is operated open-circuit instead (no current flow, open terminals), the open-circuit voltage U_oc builds up: photogenerated carriers accumulate at the contacts until the resulting opposing field exactly cancels the photo-induced diffusion current. Between these two extremes – short circuit and open circuit – lies the cell's entire usable operating range, where electrical power P = I·U is actually delivered to an external load.

Unlike the photodiode, the solar cell's active area is maximized rather than minimized: photodiodes are often small and fast, while solar cells are large (typically 15×15 cm or more for Si wafers) and optimized for maximum light collection. This area optimization brings its own challenges – particularly the lateral series resistance involved in transporting the generated current to the contacts, a topic explored further in the section on internal structure.

The classic crystalline silicon solar cell consists of a lightly p-doped base (typically boron-doped, wafer thickness 150–180 µm), into which a heavily n-doped emitter layer is diffused from the front (usually phosphorus, diffusion depth only 0.3–0.5 µm). This shallow, strongly asymmetric pn junction – the emitter much thinner and more heavily doped than the base – is designed so that as many photons as possible are absorbed at or near the depletion region, where charge separation is most efficient, while the thick base absorbs the bulk of the light across a wide spectral range.

The front side carries a contact grid of fine metal fingers (usually screen-printed silver paste, finger width often below 100 µm) plus two to three wider busbars that collect the current flowing laterally through the thin emitter layer. This grid involves a fundamental trade-off: a denser, wider finger pattern reduces the emitter's series resistance but simultaneously shades more active area, blocking incident light – the optimal finger design balances electrical against optical losses. The back side, by contrast, usually carries a full-area aluminum or silver metallization that serves simultaneously as the back contact and as a reflector for unabsorbed light.

Two further structural features specifically boost efficiency. The anti-reflective coating (ARC, usually silicon nitride Si₃N₄, thickness on the order of a quarter-wavelength of the relevant spectral range) reduces front-surface reflection losses through destructive interference of the reflected light – uncoated silicon otherwise reflects over 30% of incident light due to its high refractive index (n ≈ 3.5), while ARC reduces this to a few percent. The surface is additionally often textured (for monocrystalline silicon usually pyramid-shaped via anisotropic alkaline etching along the (111) crystal planes), so that light reflected off one pyramid facet strikes a neighboring facet and gets a second chance at absorption instead of being lost entirely. On the back side, a back surface field (BSF) – an additional, more heavily doped p⁺ layer directly beneath the back contact – creates an internal field that keeps minority carriers away from the highly recombination-active metal interface, increasing effective collection.

The electrical behavior of a solar cell can be described, in the simplest case, by the one-diode equivalent circuit: an ideal diode, in parallel with a current source for the photogenerated current I_ph, supplemented by a series resistance R_s (contact resistances, emitter and base resistance, metallization) and a shunt resistance R_p (leakage currents via crystal defects or cell edge regions). The resulting current-voltage curve under illumination runs from I_sc at U = 0 to U_oc at I = 0, with a characteristic "knee" in between – the precise shape of this knee largely determines the usable power.

On this curve lies the point of maximum power output, the maximum power point (MPP), at values I_mpp and U_mpp with P_mpp = I_mpp·U_mpp. The ratio of this maximum power to the theoretically largest possible rectangle formed by I_sc and U_oc is called the fill factor FF = P_mpp/(I_sc·U_oc) – a measure of how "square" the curve is. High-quality monocrystalline Si cells achieve fill factors of 0.80–0.83; series resistance losses round off the knee and lower the fill factor, while too low a shunt resistance mainly distorts the curve in the low-voltage region. Efficiency η = P_mpp/P_light relates the maximum electrical output power to the incident optical power (under standard test conditions, 1000 W/m², AM1.5 spectrum) and is the central figure of merit for comparing cell technologies.

Since MPP voltage and current depend on irradiance and temperature and shift continuously throughout the day, real photovoltaic systems never operate at a fixed operating point but instead use an MPP tracker (MPPT) in the inverter, which continuously samples the curve and electronically adjusts the load resistance so the cell is always operated near its current power maximum.

Even an ideal silicon solar cell cannot convert all incident solar energy into electrical power – the Shockley-Queisser limit from 1961 sets a theoretical efficiency ceiling for a single-junction solar cell with a given bandgap, around 33% for silicon (E_g ≈ 1.12 eV). Two fundamental, material-inherent losses cause this limit. Thermalization losses occur because photons with energy above the bandgap immediately release their excess energy as heat (phonons) as soon as the excited electron relaxes to the conduction band edge – for silicon this affects a substantial portion of the solar spectrum, since many photons carry considerably more energy than the 1.12 eV bandgap. Transmission losses, conversely, arise from photons below the bandgap energy that pass through the semiconductor unused, since their energy simply isn't sufficient to excite a carrier.

Beyond these unavoidable material-inherent limits, a range of technological loss mechanisms can be reduced through better cell design but never fully eliminated. Optical losses include the residual reflection already mentioned despite the ARC, shading from the front contact grid (typically 3–5% of the cell area), and incomplete light-trapping despite texturing. Recombination losses – radiative, defect-mediated (Shockley-Read-Hall), or Auger, as already discussed in the LED chapter, though here an unwanted rather than desired effect – reduce the number of carriers actually collected at the contacts, particularly at the surface and at crystal defects. Resistive losses, finally, arise at series resistances (emitter layer, metallization, contact junctions) and become quadratically more significant with rising current density (P_loss = I²·R_s), which becomes the limiting factor especially for cells under concentrated sunlight.

Crystalline silicon dominates the global photovoltaic market with a share well above 90%, divided mainly into monocrystalline cells (grown from a single silicon crystal, usually via the Czochralski process, more homogeneous crystal structure, currently achieving efficiencies around 22–24% in mass production) and multicrystalline cells (cast from multiple crystal grains, cheaper to produce, but with somewhat lower efficiencies due to grain boundaries acting as additional recombination centers). The material base is thus the same as for most wafers used in microelectronics, though with substantially lower crystal purity requirements than for integrated circuits – a cost advantage that made silicon photovoltaics economically viable at scale in the first place.

Thin-film technologies pursue a fundamentally different approach: instead of thick wafers, only an absorber layer a few micrometers thick is deposited on a low-cost carrier substrate (glass, metal foil) – possible because materials like CdTe (cadmium telluride) or CIGS (copper indium gallium diselenide) have a direct bandgap and, quite analogous to the LED material choices covered in Chapter 1, capture light over a much shorter absorption length than indirect silicon. This saves material and potentially enables cheaper manufacturing, at currently somewhat lower efficiencies than crystalline silicon.

For applications where efficiency matters more than cost per area – such as satellites or concentrating photovoltaic systems – III-V multi-junction solar cells are used, directly tying into the material systems covered in the compound semiconductor section: several pn junctions of different bandgaps (e.g., GaInP, GaAs, germanium) are grown monolithically on top of each other, so that each subcell preferentially absorbs the spectral range energetically suited to it and passes the remaining photons on to the next subcell – this concept circumvents the Shockley-Queisser limit of a single cell and achieves laboratory efficiencies above 45%. Perovskite solar cells are considered a promising but not yet long-term-stable addition, whose solution-based, potentially very low-cost fabrication is currently being intensively researched, among other things in tandem configuration with conventional silicon.