Semiconductor Technology from A to Z

A classical system-on-chip (SoC) integrates every functional block -- CPU cores, GPU, I/O controllers, memory interfaces -- onto a single monolithic die. The chiplet approach deliberately breaks this SoC apart into several smaller, functionally distinct dies ("disaggregation"), which are then reassembled into a functionally coherent system using the advanced packaging techniques described in the previous chapters (interposer, hybrid bonding).

This decomposition generally follows functional boundaries that already exist in chip design: compute cores, memory controllers, I/O blocks, and analog circuitry are typically already organized as distinct, clearly delineated modules (IP blocks) within a chip design. The chiplet approach makes this logical modularity physically usable by transferring it onto separate dies.

The central advantage lies in manufacturing yield: since a chip's defect probability grows disproportionately with its area, the yield of one large monolithic die drops drastically faster than that of several smaller dies with the same total area -- this relationship approximately follows the so-called Poisson yield model, according to which the probability of a defect-free chip decreases exponentially with area.

A defective small chiplet is discarded while the rest of the system can still be used -- with a monolithic chip, the same defect causes total failure of the entire, often significantly more expensive die. In addition, as mentioned in chapter 1, each chiplet can be produced in whichever process node is economically and technically optimal for it, instead of committing the entire chip to the most expensive process it needs -- an I/O chiplet, for instance, benefits little from the newest, most expensive logic processes and can therefore be manufactured in an older, cheaper node without compromising overall system performance.

Impact of a defect: monolithic die vs. chiplet disaggregation

These advantages come with a downside: the connection between chiplets -- even via the densest advanced packaging techniques such as hybrid bonding -- has higher latency and higher energy consumption per transmitted bit than on-chip wiring within a monolithic die. Every chip-to-chip connection, however densely packed, introduces additional parasitic capacitance, longer effective signal paths, and additional driver circuitry compared to a purely internal connection within the same die.

System architects must therefore carefully weigh which functional blocks are coupled tightly enough -- for example requiring very high bandwidth and low latency tolerance -- to benefit from monolithic integration, and which are suited, due to looser coupling or differing technology requirements, to being split into separate chiplets. This trade-off is one of the central design decisions in modern heterogeneous system architectures.

For chiplets from different manufacturers to be combined into a shared system, standardized physical and protocol-level interfaces are needed -- without such a standard, every manufacturer would remain confined to proprietary, mutually incompatible chiplet ecosystems. The industry standard Universal Chiplet Interconnect Express (UCIe) defines both the electrical layer (signal levels, pitch, bump arrangement) and the transfer protocol, with the goal of enabling a vendor-independent "chiplet marketplace" analogous to today's standard IC procurement, in which chiplets from different suppliers could be freely combined -- much as standard ICs from different manufacturers work together on a circuit board today.