Semiconductor Technology from A to Z

While 2.5D integration arranges dies side by side, true 3D stacking places several dies directly on top of one another and connects them vertically via TSVs. Two fundamental manufacturing approaches are available, differing mainly in the point at which singulation occurs:

• Die-to-die (D2D): individual dies that have already been singulated and tested are stacked on top of each other. Advantage: before stacking, each die can be individually verified as functional ("known good die"), which significantly improves the overall yield of the stack -- a defective die is simply never built in, rather than ruining an already-stacked assembly.
• Wafer-to-wafer (W2W): two complete, unsingulated wafers are bonded together as a whole and only singulated afterward. Advantage: significantly higher throughput and placement accuracy, since all dies on a wafer are bonded simultaneously in a single step. Disadvantage: a defective die on either wafer causes the entire stacked device at that position to fail, since no pre-selection is possible -- the yield losses of both wafers effectively multiply.

A hybrid approach, die-to-wafer (D2W), combines the advantages of both methods: tested individual dies are stacked onto a complete wafer, preserving known-good-die selection while at least one side of the process benefits from wafer-level throughput.

The densest form of 3D interconnect currently available is hybrid bonding. Here, both surfaces to be joined have copper areas (for the electrical connection) and oxide areas (for mechanical bonding and isolation) planarized with high precision at the same time -- using chemical-mechanical polishing, see the corresponding chapter -- and are then joined directly, without any additional solder or bump material.

The actual bonding process takes place in two phases: under pressure and moderate temperature, the oxide surfaces first fuse chemically (similar to a fusion-bonding step), which already mechanically fixes the two dies in place. Subsequently, at somewhat higher temperature, the copper expands thermally more strongly than the surrounding oxide and forms a direct metallic connection that is also electrically low-resistance. This makes it possible to achieve interconnect pitches below one micrometer -- an order of magnitude fundamentally unreachable with classical solder or bump processes, since solder always requires a minimum volume and a minimum spacing to avoid short circuits.

Hybrid bonding before and after the bonding process

Stacked dies generate heat during operation that must be conducted away through several active layers -- a die in the middle of a stack has a significantly worse thermal path to the heat sink than a single die sitting flat on a substrate, whose back side has direct contact with the heat sink. This thermal constraint is one of the main reasons why pure 3D stacking of multiple high-performance logic dies has so far seen only limited deployment.

In addition, mechanical stress caused by differing thermal expansion coefficients of the stacked materials increases with every additional layer -- similar to the TSV issue from the previous chapter, but here distributed across the entire stack area rather than localized around individual vias. Both factors limit, in practice, how many active, high-power logic dies can reasonably be stacked on top of each other, while passive or low-power memory layers (as in HBM) are far less critical, since they generate significantly less waste heat and can therefore be stacked in greater numbers of layers.