This physical isolation has direct consequences: in bulk devices, a parasitic capacitance always exists between the active region and the substrate, impairing switching speed and power consumption. In addition, neighbouring n- and p-wells together with the substrate can form a parasitic thyristor structure that, under certain conditions, triggers (latch-up), rendering the circuit non-functional or even destroying it.
With SOI, the substrate capacitance is practically eliminated, since the buried oxide layer sits in between – enabling higher switching speeds at lower power dissipation. Latch-up is structurally impossible, since no continuous semiconductor path to the substrate exists. In addition, the thin, fully isolated active layer improves short-channel behaviour: the electric field from the drain can no longer spread as easily through the substrate to the channel, reducing unwanted short-channel effects such as DIBL – an advantage modern processes exploit for further scaling, similar to the FinFET.