Semiconductor Technology from A to Z

A through-silicon via is a vertical, electrically conductive connection that runs completely through the silicon substrate of a die. Unlike classical wiring layers, which sit exclusively on the chip surface and run laterally, the TSV opens up the third dimension: signals and supply voltages can be routed from the front side of a die directly to the back side -- and thus to the next die in a stack -- without the detour via bond wires at the chip edge.

This direct vertical through-connection is the fundamental technological prerequisite for true 3D stacking (see the following chapter): only TSVs make it possible to stack several active dies on top of one another so that they function electrically almost like a single, continuous chip -- with short, direct signal paths instead of long detours via peripheral connections. For systems with high data throughput between layers, such as a logic die and an HBM stack, this short vertical path is decisive for both bandwidth and energy efficiency.

The process broadly breaks down into three approaches, which differ in when the via is created relative to the rest of the fabrication flow:

• Via-first: the TSV is etched into the bare wafer before transistor fabrication. This approach allows high-temperature-stable fill materials such as polycrystalline silicon, but is difficult to reconcile with modern CMOS processes, since the subsequent high-temperature steps of transistor fabrication place thermal and mechanical stress on the via fill.
• Via-middle: the TSV is created after transistor fabrication (FEOL) but before metallization (BEOL). This is the industrially dominant approach today, as it leaves the established, sensitive transistor fabrication untouched while still leaving enough process margin for the subsequent metallization.
• Via-last: the TSV is etched only after the chip is fully fabricated, sometimes even from the wafer back side. The advantage is complete decoupling from front-side processing -- this approach is particularly suited when TSVs need to be added retroactively to already-qualified, unchanged chip designs.

The via itself is etched using deep reactive ion etching (Bosch process, see the dry etching chapter) and reaches aspect ratios of 10:1 or higher -- typical diameters are 5–10 µm, at depths of 50–100 µm. These high aspect ratios place substantial demands on etch rate, sidewall profile, and uniformity across the entire wafer.

Since the surrounding silicon is itself semiconducting, the via wall must first be electrically isolated with a thin oxide layer (usually via PECVD, see the deposition chapter) -- without this isolation, the filled copper would be short-circuited through the substrate. This is followed by a barrier layer (typically Ta/TaN) that prevents copper from diffusing into the silicon -- the same issue encountered with copper metallization (see the copper technology chapter), only here on a much larger, deeper structure. Only after that is the via electrochemically filled with copper, usually via bottom-up electroplating to avoid trapped voids.

Structure of a TSV in cross-section

The higher the aspect ratio, the more difficult it becomes to achieve complete, void-free copper filling -- similar to the gap-fill problem in CVD processes, only on a much larger scale and with the particular characteristics of electrochemical deposition. Even small non-uniformities in current density distribution can cause the via to close off faster at the top than it fills from the bottom, trapping a void inside.

In addition, because the thermal expansion coefficient of copper differs strongly from that of silicon, the filled-in copper creates mechanical stress in the surrounding material. This stress can degrade transistor performance in the immediate vicinity of the TSV, which is why chip designers define a so-called "keep-out zone" around every TSV -- an area in which no active transistors may be placed. The size of this zone depends on the TSV diameter, the copper fraction, and the acceptable performance degradation, and must be explicitly accounted for during chip floorplanning.