Semiconductor Technology from A to Z

For decades, the semiconductor industry followed Moore's law: the number of transistors per chip doubled roughly every 18–24 months, primarily through shrinking feature sizes. This scaling path was so reliable that for generations it was treated as a law of nature for the industry, and entire business models -- from processor makers to lithography equipment suppliers -- were built on top of it.

At feature sizes in the single-digit nanometer range, however, this scaling increasingly runs into physical and economic limits that can no longer be worked around simply through better process technology. On the physical side, leakage currents rise due to short-channel effects: the shorter the channel between source and drain becomes, the harder it is to fully suppress current flow in the off state, leading to unwanted power dissipation and heat generation -- an effect addressed among other things by FinFET and gate-all-around architectures. On the economic side, lithography cost per exposure step is exploding: modern EUV systems can cost well over 200 million euros per machine, and with every additional process node the number of required mask layers and double- or multi-patterning exposure steps grows further. On top of that, yield drops disproportionately for large monolithic chips, since the probability of a defect grows statistically with chip area -- a single particle or pattern defect can render an entire large die unusable.

At the same time, demand for computing power -- driven not least by AI accelerators, whose training and inference workloads benefit from additional compute and memory capacity in a practically unbounded way -- calls for ever more transistors per system. The industry's answer increasingly lies not solely in smaller transistors but in a smarter arrangement and connection of multiple chips: advanced packaging. Rather than continuing to push back the limits of a single manufacturing process, a growing share of innovation shifts to the question of how several dies, potentially manufactured in different technologies, can be brought together into an overall system as densely, quickly, and cost-effectively as possible.

Instead of integrating every function of a system onto a single monolithic die, this approach implements individual functional blocks -- processor cores, memory, I/O, analog circuitry, RF components -- on separate chips, often manufactured in different technologies and process nodes, which are then tightly coupled into an overall system. This is known as heterogeneous integration, because it deliberately combines different process technologies -- for example the most advanced logic nodes alongside mature, cheaper memory or analog processes -- within the same system.

This strategy allows each building block to be manufactured in the technology best suited and most cost-effective for it. A typical example: logic circuits are manufactured in a state-of-the-art 3 nm process, where transistor density and switching speed matter most, while memory blocks are manufactured in a much older, more mature, and therefore cheaper node, since reliability and cost per bit take priority there. Without heterogeneous integration, a system designer would have to accept compromises for a single, shared manufacturing process -- for instance, manufacturing memory cells in a node optimized for logic but unnecessarily expensive for memory, or conversely giving up state-of-the-art logic performance to stay on the cheaper memory process.

The challenge thus shifts from the transistor to the interconnect technology between chips -- from the question that dominated for decades, "how small can a transistor become?", to the new central question, "how densely, how fast, and how energy-efficiently can two or more dies be connected to each other?" This shift in technological focus shapes the techniques covered later in this section -- TSV, interposers, and hybrid bonding -- which address exactly this interconnect problem.

The classical techniques covered in the assembly chapters -- wire bonding and flip-chip -- each connect a single die to a package or substrate. Both techniques have proven themselves over decades, but they reach their limits when faced with the demands of modern heterogeneous systems. The electrical connections sit either at the edge of the chip (wire bonding, via fine gold wires from the bond pad to the package terminal) or across the chip surface (flip-chip, via solder or copper bumps that solder the die directly to the substrate). In their achievable interconnect density, however, both techniques are limited: wire bonds typically achieve a pitch, i.e. the spacing between adjacent connections, of 40–50 µm, while flip-chip bumps are coarser at 100–150 µm. What matters here is less the pitch itself than the arrangement: wire bonds sit exclusively along the chip edge, so their number grows only with the perimeter, whereas flip-chip bumps use the entire chip area. Despite the coarser grid, flip-chip therefore achieves the considerably higher connection count. These values may seem coarse compared to nanometer-scale transistor structures, but they are limited by the mechanical and thermal boundary conditions of the respective joining process -- for example the minimum stable size of a solder ball, or the spacing needed to avoid short circuits during reflow soldering.

Advanced packaging techniques such as TSV (through-silicon via), interposer technology, and hybrid bonding, covered in the following chapters, achieve interconnect densities that are several orders of magnitude higher -- down into the sub-micrometer range, in some cases well below one micrometer pitch. Only this leap in interconnect density makes it possible to couple several dies so tightly that they behave electrically almost like a single monolithic chip -- with short signal paths, low latency, and high bandwidth between subsystems. These techniques thus form the technological foundation for the 2.5D and 3D integration described later in this section.