FPGA vs. ASIC: Synthesis Flow and HDL

There are fundamentally two paths for turning a digital circuit design into hardware. An ASIC (Application-Specific Integrated Circuit) is designed for exactly one application and manufactured as a standard-cell layout using the process steps described in earlier chapters – photolithography, etching, doping, metallization; its function is fixed and unchangeable after fabrication. An FPGA (Field-Programmable Gate Array), by contrast, consists of a grid of prefabricated but configurable logic blocks (typically lookup tables with a few inputs, combined with flip-flops) and a programmable interconnect network, whose function is only determined after manufacturing – and can be reprogrammed arbitrarily often in the field – via a configuration bitstream.

The fundamental difference therefore lies in when the function is fixed: in an ASIC, the wiring is physically cast into metal layers, while in an FPGA it is emulated electronically – with corresponding trade-offs in area, speed, and power consumption.

Both ASICs and FPGAs today are designed almost exclusively using hardware description languages (HDLs) such as VHDL or (System)Verilog, which describe the desired circuit behavior at the register-transfer level (RTL) – that is, as a data flow between registers and the combinational logic in between, without yet fixing concrete gates. A logic synthesis tool automatically translates this RTL description into a netlist of actual gates (for an ASIC, from a standard-cell library; for an FPGA, from lookup tables and flip-flops), optimizing according to given targets for area, speed, and power.

Afterward, for an ASIC, the place-and-route step handles the physical placement of cells and wiring on the chip before the mask data (GDSII) for fabrication is generated; for an FPGA, a comparable step maps the logic onto specific lookup tables and interconnect resources of the target chip before a configuration bitstream is generated, which is loaded into the FPGA at power-up. Both flows conclude with a timing analysis that ensures all paths meet the setup and hold conditions described in static timing analysis at the target frequency.