DAC Architectures

A digital-to-analog converter (DAC) generates an analog voltage or current from an N-bit digital code, selecting from 2^N possible discrete output values.

Two parameters are used to evaluate linearity: DNL (Differential Non-Linearity) describes the deviation of the spacing between two adjacent output codes from the ideal LSB step – a DNL ≤ –1 LSB results in non-monotonic behavior. INL (Integral Non-Linearity) describes the cumulative deviation of the entire transfer curve from the ideal straight line.

For dynamic evaluation, the settling time is decisive: the time required for the output to settle within a defined error band (e.g. ±½ LSB) after a code change. It limits the maximum update rate of the DAC and is influenced by the bandwidth of the output stage (often an op-amp buffer).

The R-2R DAC uses a resistor network built from only two resistor values (R and 2R), which can be cascaded to any number of bits without – unlike a binary-weighted resistor network – requiring extreme resistance ratios between the MSB and LSB. At each node of the network, a switch connects either to ground or to the reference voltage depending on the bit value.

The major advantage is good manufacturability using just two precisely matched resistor values, which reduces area and matching requirements. Achievable accuracy, however, depends strongly on the matching of the switch transistors and resistors; R-2R DACs are commonly used for resolutions in the 8–16 bit range at moderate speeds.