Semiconductor Technology from A to Z

An n-channel JFET consists of a continuous channel of n-doped semiconductor material, usually silicon. On opposite sides of the channel (in a planar layout) or surrounding it (in a symmetric layout), heavily p⁺-doped regions are introduced, which together form the gate terminal. Ohmic source and drain contacts are located at the two ends of the channel. Because the channel is physically symmetric between source and drain, the two terminals are in principle interchangeable for most JFETs – it is the external circuit that determines which terminal serves as the source (reference potential). In p-channel JFETs, the doping types and polarities are reversed accordingly.

The pn junction between gate and channel is always reverse-biased during operation (for an n-channel JFET, V_GS ≤ 0 V). This creates a depletion region that is essentially free of mobile charge carriers and therefore does not contribute to current flow. As the reverse bias increases, this region grows into the channel and narrows its conductive cross-section. Because the drain-source voltage V_DS itself produces a voltage drop along the channel, the depletion region is more pronounced at the drain end than at the source end – the channel therefore narrows in a wedge shape. Once the depletion region reaches the opposite edge at a sufficiently high voltage, the channel is completely pinched off.

The output characteristic curves (I_D vs. V_DS for various V_GS) show three distinct regions: In the ohmic (linear) region (small V_DS), the JFET behaves approximately like a voltage-controlled resistor whose resistance depends on V_GS. In the pinch-off or saturation region (V_DS > V_DS,sat), I_D remains nearly constant, since the channel is already pinched off at the drain end and further increases in voltage have little additional effect on current. The drain current in saturation can be approximated by the Shockley equation:

I_D = I_DSS · (1 − V_GS / V_p)²

Here I_DSS is the maximum drain current at V_GS = 0 V, and V_p is the pinch-off voltage. In the breakdown region (very large V_DS), avalanche breakdown eventually occurs at the drain-side pn junction, which can destroy the device.

For use as an amplifying element, the transconductance g_m = ∂I_D / ∂V_GS is the key parameter, indicating how strongly the drain current changes for a small change in gate-source voltage. Because the JFET is voltage-controlled with very low gate current, it offers an extremely high input impedance, making it – much like the MOSFET – well suited to high-impedance signal sources.

Because the gate is always reverse-biased, gate leakage current is extremely low, making JFETs a preferred choice for low-noise input stages, such as in operational amplifiers, electrometer amplifiers, and high-quality audio equipment. Other classic applications include voltage-controlled resistors (chopper circuits), simple constant-current sources (by shorting gate to source), and RF switches. Since JFETs have no sensitive oxide layer, they are more robust against electrostatic discharge (ESD) than MOSFETs. On the downside, JFETs cannot be operated in enhancement mode, and because of the lateral extent of the gate regions they scale less well than MOSFETs – which is why they play no role in highly integrated digital circuits.