Si Power Devices (Power MOSFET, IGBT)

The vertical Si power MOSFET (usually built as a DMOS – Double-Diffused MOS – device) carries current vertically through the wafer: source and gate sit on the top surface, the drain contact on the wafer backside. This geometry allows high currents in a compact chip area, since the entire chip area serves as the current cross-section. The decisive drawback appears as blocking voltage rises: on-resistance R_DS(on) grows roughly with the 2.5th power of the breakdown voltage, because silicon’s low critical field strength requires a thick, lightly doped drift layer to absorb the electric field while blocking. This relationship is exactly what underlies the Baliga figure of merit introduced in the compound-semiconductor chapter as a power-device benchmark – and explains why classic Si MOSFETs quickly become uneconomical above a few hundred volts.

Starting in the mid-1990s, superjunction technology (known under brand names such as CoolMOS) partially broke this relationship. Instead of a uniformly lightly doped drift region, narrow p- and n-columns are alternately introduced that mutually deplete each other laterally when blocking (“charge balancing”). This allows the n-drift region to be doped considerably more heavily without reducing breakdown voltage – R_DS(on) then scales only roughly linearly with voltage instead of by a high power. Superjunction MOSFETs today dominate the roughly 500 to 900 V range (switched-mode power supplies, PFC stages) and are therefore silicon’s strongest competitor to GaN HEMTs in this voltage window – though with lower switching frequency due to higher output capacitance. The gate itself is unaffected: as in a classic power MOSFET, it sits at the very top surface and controls the channel in the uppermost p-well, which is electrically connected to the p-columns beneath it. The columns themselves carry no channel – they exist solely to shape the field in the drift region. Because the columns are 40 to 60 µm deep, ordinary diffusion or implantation cannot produce them. The trench-fill process has become the standard approach: a deep, narrow trench is dry-etched into the finished n-epitaxial layer (deep reactive ion etching) and then epitaxially refilled with p-doped silicon, followed by CMP planarization of the surface. Older process generations instead used multi-epitaxy: several thin epitaxial steps each with local p-implantation, which only merge into a continuous column during a final high-temperature diffusion – more process steps, but without the demanding trench etch.