Static Timing Analysis: Setup and Hold Time

Static timing analysis (STA) checks whether a digital circuit operates reliably at a given clock frequency without actually running the circuit as in a simulation. To do this, every path between two consecutive flip-flops is examined: the launching flip-flop produces its value at the output after the clock-to-Q delay t_CQ – typically in the range of 20 to 100 picoseconds depending on technology and cell –, the value then propagates through the combinational logic with delay t_logic, and must arrive at the data input of the capturing flip-flop before it can be latched.

For the capturing flip-flop to sample the value correctly, the signal must already be stable for a certain time before the active clock edge (setup time t_setup, often 20 to 50 ps) and must not change for a certain minimum time after the clock edge either (hold time t_hold, often just a few picoseconds up to about 20 ps). If these timing windows are violated, the flip-flop can enter a metastable state in which the output oscillates between the two logic levels for an indefinite time.

The setup check ensures that a signal arrives at the destination register in time before the next clock edge. For a clock period T with clock skew Δt_skew between the launching and capturing flip-flop, the condition is T + Δt_skew ≥ t_CQ + t_logic + t_setup. The difference between the available time and the time actually required is called the setup slack; if the slack is negative, the path violates the required clock frequency and must be fixed using faster cells, fewer logic stages, or a reduced clock frequency. For example, with a clock period of 1 ns (corresponding to 1 GHz), a t_CQ of 40 ps, a logic delay of 700 ps, and a setup time of 30 ps, the resulting slack is about 230 ps – clearly positive and therefore not critical.

The critical path of a circuit is the path with the smallest setup slack; it determines the maximum possible clock frequency of the entire chip. Because manufacturing variation, supply voltage, and temperature all affect gate delays, which can vary by 20 to 30 %, the setup check is always performed for the slowest specified process, voltage, and temperature condition (the slow corner).