Semiconductor Technology from A to Z

Dynamic power dissipation arises from charging and discharging the parasitic load capacitance of a gate during a switching event and is described by P_dyn = α · C_L · V_DD² · f, where C_L is the load capacitance, V_DD the supply voltage, f the clock frequency, and α the switching activity, that is, the fraction of clock cycles in which the gate actually switches, typically around 0.1 to 0.3 in real logic circuits. For a gate with C_L = 1 fF, V_DD = 0.8 V, f = 2 GHz, and α = 0.2, the resulting dynamic power is about 0.26 µW – multiplied across several hundred million gates on a modern chip, this quickly adds up to a total power in the watt range. Because power scales quadratically with supply voltage, lowering V_DD is one of the most effective ways to reduce dynamic power, though it is limited by the minimum voltage required for reliable switching.

In addition to the charging power itself, dynamic power also includes short-circuit power, which arises during the finite rise and fall time of a signal when the PMOS and NMOS paths of a CMOS gate briefly conduct at the same time, contributing 10 to 20 % of total dynamic power depending on edge steepness. It can be kept low through sufficiently steep signal edges, that is, adequate drive strength in the preceding stage.

Even when a CMOS gate is not switching, a small residual current flows that is no longer negligible at small feature sizes and determines the static power dissipation. The dominant contribution is subthreshold leakage current, which still flows even when the gate-source voltage is below the threshold voltage because the channel is not fully turned off; it grows exponentially as threshold voltage decreases and temperature increases, characterized by the subthreshold swing, which in real MOSFETs is about 70 to 100 mV per decade of current change, compared to a theoretical minimum of about 60 mV/decade at room temperature.

Further contributions come from gate leakage current through the increasingly thin gate oxide and from reverse-bias current through the drain and source p-n junctions. Because modern technologies use lower threshold voltages, often only 0.2 to 0.3 V, to retain adequate switching speed as supply voltage decreases, the share of leakage power in total power dissipation grows with every technology generation and can already reach 20 to 40 % of a chip total idle power in advanced processes.

Clock gating selectively disables the clock supply to circuit blocks that are not needed in the current operating state, preventing unnecessary switching activity and therefore dynamic power without altering the stored state of the affected registers; typical designs can save 10 to 30 % of total dynamic power this way. Power gating goes a step further and completely disconnects entire circuit blocks from the supply voltage using switch transistors (header or footer switches), which additionally reduces the static leakage power of those blocks by one to two orders of magnitude, though the stored state is lost unless it was saved beforehand in a separate retention flip-flop.

Multi-V_t design places transistors with different threshold voltages on the same chip: cells on timing-critical paths receive a low threshold voltage for high switching speed, while non-critical cells use a high threshold voltage with correspondingly much lower, often an order of magnitude lower, leakage current. Dynamic voltage and frequency scaling (DVFS) adjusts supply voltage and clock frequency at runtime to match the computational load actually required: halving both voltage and frequency theoretically reduces dynamic power to one-eighth, making DVFS especially effective for energy savings under partial load in mobile processors.