Semiconductor Technology
from A to Z
Everything about semiconductors and wafer fabrication
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Chapter
Fundamentals
The atomic structure
The elements, the periodic table
Chemical bonds
Noble gases
Conductors – Insulators – Semiconductors
Doping: n- and p-semiconductors
The p-n junction
Transistors and Memory
Wafer Fabrication
Silicon
Production of raw silicon
Fabrication of the single crystal
The wafer
Doping techniques
Oxidation
Overview
Fabrication of oxide layers
LOCOS technology
Deposition
Plasma, the fourth aggregation state of a material
Chemical vapor deposition
Physical deposition methods
Metallization
Requirements on metallization
Aluminum technology
Copper technology
Metal semiconductor junction
Wiring
Photolithography
Exposure and resist coating
Exposition methods
Photoresist
Development and inspection
Photomasks
Optical Proximity Correction (OPC)
Wet Chemistry
Etch processes
Wet etching
Wafer cleaning
Dry Etching
Overview
Dry etch processes
Reactor Types
Compound Semiconductors and High-k Materials
Compound Semiconductors
Fundamentals & Material System
Crystal Growth & Substrates
SiC Power Devices
GaN Power Devices
Applications & System Comparison
Metrology
Film thickness measurement
Particle inspection
Wafer Test
Wafer Test
Final Test and Binning
Assembly
Dicing
Die Attach
Bonding
Encapsulation
Devices
Field-effect transistors
Bipolar transistors
Construction of a FinFET
DRAM Fabrication: The Trench Capacitor Process
Digital technology
From transistor to logic gate
The CMOS Fabrication Flow
The SRAM Cell
The DRAM Cell
The Flash Memory Cell
Design Rules
Layout versus Schematic (LVS)
Circuit Layouts
Micromechanics
Introduction to MEMS
Anisotropic Etching of Silicon
Sacrificial Layer Technique
Bulk vs. Surface Micromachining
The MEMS Accelerometer
The Microphone and Pressure Sensor
DRIE: Deep Reactive Ion Etching
Process Flow
Supply Chain
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32 nm
22 nm
16 nm
11 nm
7 nm
5 nm
3 nm
2 nm
Akronyms
Statistics
Bit per euro (DRAM)
Evolution of the gate length of MOSFETs
Exposure wavelength vs. critical dimensions
FLOPS: floating point operations
Intel:AMD - CPU clock
Intel:AMD - Number of transistors
Intel:AMD - Process development
Manufacturing costs for different technology nodes
Manufacturing costs per transistor
Millions of instructions per second
Number of calculations per second per 1000 euro
Number of manufactured bits
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Fundamentals
The atomic structure
The Atomic Model
Orders of Magnitude
The elements, the periodic table
The Elements
The Periodic Table of the Elements
Chemical bonds
Tendency to Form Bonds
The Covalent Bond
The Ionic Bond
The Metallic Bond
Weak Bonds
Noble gases
Conductors – Insulators – Semiconductors
Conductors
Insulators
Semiconductors
The Band Model
Doping: n- and p-semiconductors
Doping
n-Type Doping
p-Type Doping
Band Diagram of Doped Semiconductors
The p-n junction
The p-n Junction in Equilibrium
The p-n Junction with an Applied Voltage
Transistors and Memory
MOSFET
Bipolar Transistor
FinFET
DRAM Cell
Wafer Fabrication
Silicon
Production of raw silicon
Starting Material: Silicon Dioxide
Purification of the Raw Silicon
Zone Refining
Fabrication of the single crystal
The Single Crystal
Czochralski Crystal Growing Process
Crucible-Free Float-Zone Growing
The wafer
Wafer Slicing and Surface Finishing
Historical Development of Wafer Size
Why Are Wafers Round?
Doping techniques
Doping
Diffusion
Diffusion Methods
Ion implantation
Oxidation
Overview
Application of Oxide Layers
Properties of oxide layers
Fabrication of oxide layers
Thermal oxidation
Oxidation by vapor deposition
LOCOS technology
Very large-scale integration
Bird's beak
Shallow Trench Isolation
Deposition
Plasma, the fourth aggregation state of a material
Plasma state
Plasma generation
Chemical vapor deposition
Silicon vapor phase epitaxy
CVD process: Chemical Vapor Deposition
APCVD: Atmospheric Pressure CVD
LPCVD: Low Pressure CVD
PECVD: Plasma Enhanced CVD
ALD: Atomic Layer deposition
Gap fill
Physical deposition methods
MBE: Molecular beam epitaxy
Evaporating
Sputtering
Metallization
Requirements on metallization
Aluminum technology
Aluminum and aluminum alloys
Diffusion in silicon
Electromigration
Hillocks
Copper technology
Copper technology
Damascene process
Low-k technology
Limits of copper wiring
Metal semiconductor junction
Contacting doped semiconductors
n-type semiconductor contact
p-type semiconductor contact
Band model of a p-n junction
Wiring
Multilayer wiring
BPSG reflow
Reflow back etching
Chemical mechanical polishing
Contacting the metallization layers
Photolithography
Exposure and resist coating
Overview
Applying an adhesion promoter
Coating
Exposure
Exposure methods used
Multipatterning
Exposition methods
Overview
Contact exposure
Proximity exposure
Reducing projection exposure
Electron beam lithography
X-ray lithography
Additional methods
Photoresist
Photoresist
Chemical composition
Development and inspection
Development
Inspection
Resist removal
Photomasks
Mask technology
Photomask manufacturing
Mask types
Next-generation lithography
Optical Proximity Correction (OPC)
Introduction & Motivation
Typical Print Errors Without Correction
Mask Bias & Serifs
Sub-Resolution Assist Features
Rule-based vs. Model-based OPC
Verification: Lithography Simulation & Process Window
Limits and Outlook
Wet Chemistry
Etch processes
Wet etching
Principle
Requirements
Dip etching
Spray etching
Anisotropic etching of silicon
Etch solutions for isotropic etching
Drying the wafers
Wafer cleaning
Cleanroom
Types of contamination
Microscopic contamination
Molecular contamination
Alkaline and metallic contamination
Cleaning techniques
Dry Etching
Overview
General
Key parameters in dry etching
Dry etch processes
Dry etch processes
Ion beam etching
Plasma etching
Reactive ion etching
Etch gases used in dry etching
Special Case: Bosch Process (Deep Reactive Ion Etching)
Reactor Types
General: Structure of a Dry Etch Tool
Reactor Types: CCP and ICP in Practice
Electron Cyclotron Resonance (ECR)
Wafer Chuck: Temperature Control and Electrostatic Clamping
Compound Semiconductors and High-k Materials
Why These Materials Are a Special Case
III-V Compound Semiconductors (GaAs, InP, GaN)
Silicon Carbide (SiC)
High-k Dielectrics (HfO₂ and Others)
Compound Semiconductors
Fundamentals & Material System
Why Compound Semiconductors for Power Electronics?
Material Comparison: SiC, GaN and Silicon
The Baliga Figure of Merit
Positioning: Where Is Each Material Used?
Crystal Growth & Substrates
SiC Crystal Growth: Physical Vapor Transport
Polytypes: Why 4H-SiC?
GaN Epitaxy: Heteroepitaxy Instead of Native Substrates
Lattice Matching, Strain and Defect Density
SiC Power Devices
The SiC Power MOSFET
The SiC Schottky Diode
Trench vs. Planar SiC MOSFET
The SiC/SiO2 Interface as a Challenge
GaN Power Devices
The 2DEG: Foundation of the HEMT
The GaN HEMT as a Power Switch
E-Mode vs. D-Mode and the Cascode Configuration
Lateral vs. Vertical: Why GaN Mostly Stays Lateral
Applications & System Comparison
E-Mobility: SiC Dominates the Traction Inverter
Fast-Charging Infrastructure and Power Supplies: GaN Excels at High Frequency
Efficiency and Switching Frequency Comparison
Cost Trends and Outlook
Metrology
Film thickness measurement
Metrology
Interferometry
Ellipsometry
Evaluation of the Measurement
Particle inspection
Metrology
Laser Scattering Measurement
Wafer Map and Classification
Review with the Scanning Electron Microscope (SEM)
Evaluating the Measurement
Wafer Test
Wafer Test
Fundamentals of Wafer Testing
The Probe Card
Yield Mapping and Redundancy
Final Test and Binning
The Final Functional Test
Burn-in
Binning
Assembly
Dicing
From Wafer to Individual Chip
Sawing Methods
Challenges and Quality Assurance
Die Attach
Mechanical Mounting of the Die
Bonding Materials
Mechanical Stress and Quality Assurance
Bonding
Electrical Contacting of the Die
Flip-Chip Technology
Requirements and Heat Dissipation
Encapsulation
Purposes of Encapsulation
Materials and Methods
Heat Dissipation and Final Quality Inspection
Devices
Field-effect transistors
Fundamentals
Fabrication of an n-Channel FET
Bipolar transistors
Fundamentals
Fabrication of an NPN Bipolar Transistor
Construction of a FinFET
General structure and mode of operation
Construction of a FinFET in a bulk process
From FinFET to nanosheet
DRAM Fabrication: The Trench Capacitor Process
General Structure and Operating Principle
Trench Capacitor Fabrication
Access Transistor and Interconnect Fabrication
Digital technology
From transistor to logic gate
The Transistor as a Switch
NMOS and PMOS Compared
The Inverter — the First Gate
Building AND from Transistors
Logic Gates Overview
The CMOS Fabrication Flow
Front-End and Back-End of Line
Wafer and Wells
Transistor Fabrication in the FEOL
Doping and Silicidation
Contacts
Metallization in the BEOL
The Flow at a Glance
The SRAM Cell
Vom Schaltbild zum Chip: EDA
Two Cross-Coupled Inverters as the Storage Core
The Access Transistors
Writing
From a Single Bit to an Array
Reading
The DRAM Cell
A Capacitor Instead of Six Transistors
Access Transistor, Word Line, and Bit Line
Leakage and Charge Decay
The Refresh Cycle
The Sense Amplifier
DRAM versus SRAM
The Flash Memory Cell
Structure of the Floating-Gate Cell
Programming and Erasing
NOR vs. NAND Architecture
Multi-Level Cell (MLC/TLC)
Comparison: DRAM, SRAM, and Flash
Design Rules
Introduction & Motivation
Basic Rule Types
Lambda-based vs. Absolute Rules
Example Rule Set
Latchup and Well Rules
Antenna Rules
Density Rules (CMP)
Design Rule Check (DRC)
Layout versus Schematic (LVS)
Introduction & Motivation
Netlist Extraction from the Layout
The Reference Netlist from the Schematic
The Comparison Algorithm
Typical Mismatches
LVS in the Design Flow
Circuit Layouts
From Schematic to Layout
Layer 1: Active Areas
Layer 2: Polysilicon
Layer 3: Contacts
Layer 4: Metal-1
Layer 5: Metal-2
Layer 6: Metal-3 — Complete
Micromechanics
Introduction to MEMS
Introduction to MEMS
Miller indices
Anisotropic Etching of Silicon
Crystal Orientation and Etch Rates
The Characteristic 54.74° Angle
(110) Silicon: Vertical Walls
Sacrificial Layer Technique
The Principle of the Sacrificial Layer
Process Flow: Deposit, Pattern, Release
Stiction: Sticking of Released Structures
Bulk vs. Surface Micromachining
Bulk Micromachining: Etching Into the Depth
Surface Micromachining: Building Up on the Surface
Which Process for Which Application?
The MEMS Accelerometer
Structure: Seismic Mass and Springs
Capacitive Readout: The Comb Structure
From Capacitance Change to Signal
The Microphone and Pressure Sensor
Shared Principle: Membrane Over a Cavity
The MEMS Microphone: Membrane and Backplate
The MEMS Pressure Sensor: Piezoresistive Readout
DRIE: Deep Reactive Ion Etching
The Limits of Wet Etching
The Bosch Process: Alternating Etch and Passivation
Scallops: The Characteristic Wavy Structure
Aspect Ratio and Process Limitations
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Content
Fundamentals
Wafer Fabrication
Oxidation
Deposition
Metallization
Photolithography
Wet Chemistry
Dry Etching
Compound Semiconductors
Metrology
Wafer Test
Assembly
Devices
Digital technology
Micromechanics