Three recent studies highlight very different parts of the semiconductor stack: interconnect insulation, high-temperature power logic, and dielectric engineering for vertical channel transistors. The common thread is materials control at dimensions where only a few atomic layers decide whether a structure works at all.
At the National University of Singapore, researchers reported an atom-thin amorphous carbon film intended to insulate ever thinner copper interconnects. The layer kept a dielectric constant of 1.35 across thicknesses from 0.8 nm to 2.7 nm, blocked copper ion diffusion, and held off electric fields of 28-31 MVmegavoltVoltage unit equal to one million volts./cm before breakdown. It was grown by chemical vapor deposition below 300 C directly on silicon dioxide, copper, and cobalt, with uniform coverage on a four-inch wafer and over sidewalls and corners of patterned features.
The same film combines low-k insulation and a copper barrier in one layer. The team said it will next work with TSMCTaiwan Semiconductor Manufacturing CompanyTSMC is named as a founding partner of the EPIC Center. to assess long-term reliability, scalability, and process compatibility. That follow-up matters because the deposition results already suggest the material can be integrated on metal and dielectric surfaces used in interconnect processing, rather than only on ideal test structures.
In a separate result, Kyoto University researchers developed silicon carbide complementary JFETs that can operate at 600 C. The device uses a bottom-gate design to improve threshold voltage control and well-based isolation instead of a semi-insulating substrate to suppress high-temperature leakage. According to the report, the leakage current was pushed close to the theoretical limit for SiCsilicon carbideSiC is one of the power semiconductor materials being assigned a distinct role in the power delivery chain., and the next step is to build more complex circuits and scale toward wafer-level production.
KAIST and UNIST also reported a multilayer SiN/SiO2silicon dioxide/SiN interlayer dielectric for oxide vertical channel transistors. The stack acts as an oxygen tunnel that compensates oxygen vacancies in the oxide semiconductor while limiting unwanted electrode oxidation, which improved current density and retention. After more than ten million cycles of electrical stress testing, threshold-voltage shift stayed below 50 mV, and the oxide semiconductor was integrated with conventional silicon CMOS1. complementary metal-oxide semiconductorCircuit technology combining n- and p-channel MOS transistors for low static power consumption.2. complementary metal-oxide-semiconductorCMOS is a fundamental semiconductor technology for digital and analog circuits. technology.