Chip design teams are increasingly moving analysis and decision-making earlier in the flow, but the result is not a simple acceleration of today’s linear process. The emerging model is more iterative: digital twins, AIartificial intelligence agents, surrogate models, and multi-physics simulation are pulling architectural and implementation choices forward, while also exposing new verification and trust problems.
One major shift is that earlier exploration now extends beyond traditional digital design. Multi-physics models are being used to build surrogate models for technologies involving different materials, and that approach is beginning to reach CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices.-level discussions as well. Earlier work can now include choices at the level of materials, transistor structures, and chip architectures.
At the same time, moving work left does not remove bottlenecks. The central question is whether AIartificial intelligence-generated designs and surrogate models are trustworthy representations of the intended hardware. Verification still requires human responsibility, especially when tools are used to reason about specifications, architecture options, or optimized PPA1. power, performance, and areaPPA is the main optimization target for advanced-node designs.2. power, performance, area. Functional verification is increasingly treated alongside security, functional safety, and power as a core design problem.
Another recurring issue is that specifications are often incomplete. Some teams are pushing toward spec-to-silicon flows and trying to extract requirements from documents, but in many cases those documents do not exist in a usable form. That makes trust and validation central blockers for agentic AIartificial intelligence flows, even where formal proofs are used early to bridge the gap.
The discussion also suggests that shift left is becoming less about locking down requirements far in advance and more about making adjustments as new information arrives. Instead of assuming a fixed target six or nine months ahead, teams may define a general direction and then refine implementation choices later, creating what is effectively an agile version of shift left.
That is particularly relevant for CPUcentral processing unitMain processor that executes program instructions and performs data operations.s, GPUgraphics processing unitA GPU is a parallel graphics processor widely used for AI acceleration.s, machine learning chips, and other designs where the eventual workload is uncertain. Several verification stages — including formal, simulation, virtual prototyping, emulation, and FPGAfield-programmable gate arrayReconfigurable logic device whose internal circuits can be programmed after manufacturing.-based work — may need to move earlier in the pipeline if teams want to reduce debug time and improve the quality of early decisions.
The practical consequence is that AIartificial intelligence agents are being used more like junior engineers than decision-makers. They can help explore options, rewrite designs for better PPA1. power, performance, and areaPPA is the main optimization target for advanced-node designs.2. power, performance, area, and surface bottlenecks faster, but the final model still has to be verified against the intended hardware. The design flow is therefore becoming more circular, with repeated refinement rather than a one-way march to a frozen specification.