Statistical surrogate methods challenge Monte Carlo in analog IC signoff

August 11, 2026

Statistical surrogate methods challenge Monte Carlo in analog IC signoff

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At sub-5 nm nodes, analog and mixed-signal signoff has reached a point where traditional corner analysis and brute-force Monte Carlo no longer deliver both fast convergence and usable insight into tail-yield behavior. A new paper discussed by EDN presents QUINSIM’s Analog Uncertainty-Aware Design (AUAD) platform as an alternative that treats uncertainty as a primary design object rather than a late verification burden.

AUAD wraps existing SPICEsimulation program with integrated circuit emphasis and TCADtechnology computer-aided designSoftware-related method or tool for development, control or data processing. tools as black boxes and builds a workflow around four stages: statistical characterization of foundry data, adaptive surrogate construction, analytical sensitivity extraction and robust optimization. The platform uses non-parametric density estimates or heavy-tailed distributions for marginals, then models parameter dependence with R-vine copulas. A Rosenblatt transformation maps those correlated inputs into a space where polynomial chaos methods can be applied.

The core surrogate is a sparse polynomial chaos expansion, trained with roughly 100 to 500 simulator calls in regions that matter most. Once trained, the model evaluates in microseconds and can support post-hoc Monte Carlo with 106 to 108 samples at negligible additional cost. From the same coefficients, AUAD derives Sobol first-order and total-effect sensitivity indices without extra simulations.

EDN highlights several benchmark cases. For a 5 nm SRAM1. static random access memoryMemory technology or system for temporarily or permanently storing digital information.2. static random-access memorySRAM is used here as a test vehicle for embedded memory performance. bit-cell, QUINSIM reports a 57-parameter model trained with 350 adaptive Spectre calls, recovering the 5σ static-noise-margin tail and identifying Tox, Vth_PMOS1. positive channel metal-oxide semiconductor2. p-channel metal-oxide-semiconductorThe p-channel device type used in the stacked CFET structure. and Leff as dominant drivers. In an FDSOI LNA/VCO case, a Student-t copula captures nonlinear Vth–DVT0W dependence and reveals a bimodal noise-figure distribution that Gaussian models miss.

Other examples include a 150-parameter SAR ADC1. analog-to-digital converterCircuit that converts an analog input signal into digital values.2. automated data collectionSystem or method for collecting, storing, exchanging or analyzing data.3. automatic defect classificationMeasurement or inspection concept for tracking defects and process variations in manufacturing. model for ENOB, where 600 adaptive simulations produce the full distribution in about 8 hours, and an optimization stage based on efficient global optimization with a Kriging meta-model and expected improvement acquisition function. Across the examples, AUAD is presented not as a faster Monte Carlo replacement, but as a statistical design flow that can expose failure modes, parameter ranking and yield surfaces directly from the surrogate model.

Source: EDN

More background: Analog Design

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