AIartificial intelligence is already pushing chip design and verification toward a different operating model, but the speakers on Semiconductor Engineering’s panel said the long-term outcome is still unclear. The discussion focused on how generative AIartificial intelligence changes engineering roles, what it means for trust and verification, and where the economic value may move as design flows become more automated.
Cindy Cui of ChipAgents said GenAI can generate millions of options quickly, which raises the importance of human judgment and system-level supervision. She described a future in which the old boundaries between design, verification, layout, and package design become less distinct, and engineers must learn new domains faster while directing AIartificial intelligence agents with confidence. Wally Rhines of Silvaco argued that learning curves still apply, even if the cost metric shifts from transistor cost to computational capability.
Verification and safety were a central theme. Shelly Henry of Moores Lab AIartificial intelligence said AIartificial intelligence systems can remain opaque even when their underlying math is studied in detail. Dave Kelf of Breker Verification Systems stressed that experienced engineers need enough understanding to trust the tools, while newer engineers may simply learn to use them. Vince Wong of Verific said the practical answer is containment: sandboxing, permissions, auditing, and recovery mechanisms that limit agent scope and preserve traceability.
The panel also warned against evaluating AIartificial intelligence tools with the same data used for training. Cui said benchmark data must reflect real design cases and increasingly complex scenarios if agentic AIartificial intelligence systems are to be validated properly. She also noted that the main risk is not only wrong output, but output that looks correct. Wong added that LLM1. local linear models2. Large Language ModelThe model class referenced in the long-context serving demo.-based systems should be constrained to human-readable communication, such as JSON, to avoid hidden or optimized machine-only exchanges.
On economics, the speakers said AIartificial intelligence could shift where value is created, but not eliminate the existing semiconductor value chain. Rhines said EDA1. electronic design automationSoftware tools for designing, simulating, verifying and laying out electronic circuits.2. equipment data acquisitionSystem or method for collecting, storing, exchanging or analyzing data. has traditionally been funded as a fixed share of R&D budgets, while Cui pointed out that a separate AIartificial intelligence budget is emerging in the industry. Ann Wu of Silimate said the long-term impact will also depend on fab capacity, noting that TSMCTaiwan Semiconductor Manufacturing CompanyTSMC is named as a founding partner of the EPIC Center.’s ramp for the AIartificial intelligence market has been a key constraint. Rhines added that future chip differentiation may move toward morphable architectures that can reconfigure connectivity, memory partitioning, and instruction sets during operation.