AMD has announced Versal tamper-resistant (TR) devices that are designed to protect security-critical information against sophisticated physical attacks while retaining the heterogeneous processing capabilities of the Versal AIartificial intelligenceAI stands for artificial intelligence Edge Series Gen 2 family. The company describes the devices as the first adaptive SoCs or FPGAfield-programmable gate arrayReconfigurable logic device whose internal circuits can be programmed after manufacturing.-based devices with built-in protection against physical attacks on the silicon backside.
At the center of the approach is a sensor-based protection die that is bonded to the main compute die using 3D active-on-active technology. The protection layer shields the full backside of the device, monitors for physical attacks and can prevent boot if the protection die is tampered with or removed.
AMD combines that physical protection with embedded CPUcentral processing unitMain processor that executes program instructions and performs data operations.s, AIartificial intelligenceAI stands for artificial intelligence Engines and programmable logic. The devices are intended to strengthen protection for security-critical information without giving up system performance, size, weight, power or time to market.
The security stack also includes expanded hardware acceleration for post-quantum cryptography. Support now covers Module-Lattice-Based Digital Signature Algorithm (ML-DSA1. display system activity2. dimensionally stable anodeElectrode designed to maintain its dimensions during electrochemical operation.) and Stateless Hash-Based Digital Signature Algorithm (SLH-DSA1. display system activity2. dimensionally stable anodeElectrode designed to maintain its dimensions during electrochemical operation.), together with hybrid boot flow support that allows multiple signature algorithms.
Additional safeguards include improvements to the application security unit (ASU) key vault and a new memory element aging sensor (MEAS) for cryptographic keys. AMD also says glitch detection has been expanded by combining an improved Versal architecture glitch detector with a new orthogonal glitch detector that increases coverage for glitches occurring simultaneously across two voltage rails.
Performance figures for the Versal TR portfolio include up to 229000 DMIPS of scalar compute, up to 369 INT88-bit integerINT8 stands for 8-bit integers and is often used for efficient AI inference. TOPS1. Tera Operations Per SecondA metric used to describe the peak operation rate of an AI accelerator.2. trillion operations per secondTOPS indicates how many trillion operations per second a chip can perform. and up to 543000 LUTs. The portfolio includes the 2VE3358TR, 2VE3558TR and 2VE3858TR devices, and each has a footprint-compatible standard counterpart so designs can move from the standard platform to the tamper-resistant version without rerunning synthesis or place and route.
Sampling is expected in the second half of 2027, with production planned for the first half of 2028. AMD notes that the devices are meant to reduce the need for separate compute, security and enclosure-based protection components in designs where physical security is a key requirement.