Co-packaged optics is moving from long-term promise into concrete production planning. At Ayar Labs’ invitation-only CPOco-packaged opticsOptical devices and CPUs are integrated into a single package Summit, speakers from Meta, Broadcom, AMD, MediaTek, Lumentum, Wiwynn and Upscale AIartificial intelligence examined what the optical interconnect ecosystem must deliver to support AIartificial intelligence infrastructure at scale, with the industry now focused less on the concept itself than on manufacturability, supply-chain readiness and standards.
The event was framed around a 2028 demand surge for co-packaged optics and the role of the Optical Compute Interconnect Multi-Source Agreement, or OCIOptical Compute InterconnectOCI is an optical interface effort aimed at enabling interoperable high-bandwidth links between systems. MSAMulti-Source AgreementAn MSA defines a common specification that allows multiple vendors to build interoperable components., in aligning the market around a common optical interface. The discussions also reflected a broader shift in emphasis: silicon photonics is no longer being positioned only as a future replacement for copper, but as a system-level requirement for scaling AIartificial intelligence workloads.
One central message was that copper interconnects are running into practical limits as speed and reach increase. MediaTek’s Bhushan Chitlur pointed to rising loss with both frequency and distance, citing about three meters at 100G signaling, around one meter at 200G, and less than a quarter meter at 400G. In optics, he said, loss is decoupled from distance, enabling scale-up networks to extend beyond a single rack.
The same logic applies at the switch level. Upscale AIartificial intelligence’s Barun Kar described co-packaged optics as a way to improve form factor and increase switch radix, while noting that radix scaling still depends on process technology, chiplet integration and thermal limits. Several speakers stressed that adoption will depend not only on bandwidth, but on operability: test, monitoring, service workflows and multivendor interoperability must all be solved before optical links can be deployed with the confidence of copper.
Integration also changes the economics for ASICapplication-specific integrated circuitIntegrated circuit customized for a specific task vendors. Chitlur said that once optics are integrated, a component becomes part of a system, and a failed optical engine after attach can force otherwise functional silicon to be discarded. He pointed to the value of HBM1. human body modelESD test model that simulates a person discharging static electricity into a component.2. High Bandwidth MemoryHBM is a stacked DRAM architecture designed to provide very high memory bandwidth. on large AIartificial intelligence ASICapplication-specific integrated circuitIntegrated circuit customized for a specific tasks and argued that yields at both the component and package-attach level must be near perfect. Thermal behavior adds another hurdle, since XPU1. accelerator processing unitXPU is used here for the compute package that hosts multiple processing elements.2. accelerated processing unitA collective term for a high-performance processor in the package architecture described. power can swing sharply and optics are highly temperature sensitive.
Rack-level design priorities were similar. Wiwynn’s Harold Liu highlighted thermal management, power delivery, serviceability and optical loss, and said volume production will require design for manufacturing from the outset, cleaner assembly environments and more automation. Lumentum’s Matt Sysak added that constraints are not limited to lasers, but also include substrates, materials, connectors and fiber, turning a historically niche laser supply chain into one that must support high-volume manufacturing.
Standardization was a recurring theme. Kar called for a common MSAMulti-Source AgreementAn MSA defines a common specification that allows multiple vendors to build interoperable components. and said the market needs a large anchor customer. Chitlur argued that single-source programs are not viable and asked for interoperability testing comparable to PCIePeripheral Component Interconnect ExpressPCIe is the high-speed serial interconnect standard plugfests. On the OCIOptical Compute InterconnectOCI is an optical interface effort aimed at enabling interoperable high-bandwidth links between systems. panel, Meta’s Drew Alduino said hyperscalers need endpoints from different suppliers to interoperate and argued that the specification should standardize as little as possible so vendors can keep room for innovation.
Broadcom’s Near Margalit described multiwavelength operation as the key technical principle behind OCIOptical Compute InterconnectOCI is an optical interface effort aimed at enabling interoperable high-bandwidth links between systems., because more wavelengths lower the per-wavelength data rate and system power. He pointed to microrings as a suitable device because of their wavelength selectivity, while AMD’s Matt Streshinsky said the technical ingredients are already available and the remaining challenge is engineering execution across multisource, multivendor and multifoundry supply. Alduino also outlined a roadmap from OCIOptical Compute InterconnectOCI is an optical interface effort aimed at enabling interoperable high-bandwidth links between systems. Gen 1, which uses four wavelengths at 50G on a standard FR41. flame-retardant 4FR4 is the standard PCB material referenced for the OCI Gen 1 grid.2. Flame Retardant 4FR4 is a widely used printed circuit board material based on glass-fiber epoxy. grid, toward Gen 2 and a five-generation path already shown to scale from 200G to 3.2T.
The summit’s overall message was that optical interconnect is entering a phase where scale, packaging, interoperability and manufacturing discipline matter as much as device performance. Ayar Labs’ Mark Wade closed by stressing that the remaining task is to move proven optics technologies into tier-one, high-volume production.