Researchers at Heidelberg University have introduced a unified interconnection network intended to scale the BrainScaleS-2 neuromorphic architecture with chiplets. The work, published as A Unified Interconnection Network for Chiplet-Based Scaling of the BrainScaleS Neuromorphic System, focuses on the routing layer needed to connect multiple BSS-2 units.
The central technical point is the separation of two traffic types within one network: error-tolerant traffic, such as spikes, and error-intolerant traffic, including configuration data and information exchanged by the processing units. According to the abstract excerpt, the proposed routing chiplet is designed to handle both classes without requiring separate interconnect concepts for each.
The architecture extends BrainScaleS-2 by enabling multiple BSS-2 units to be connected in a 2D mesh topology. That choice gives the system a defined structure for chiplet-to-chiplet communication while keeping the interconnect logic unified across the network.
The paper frames chiplet-based design as a practical way to overcome scaling limits of analog designs, citing cost and flexibility advantages over monolithic scaling. In that context, the routing chiplet is the key element that makes a multi-chip BSS-2 system technically feasible.