History-Aware RL Reduces Routing Violations in Dense Chip Layouts

September 19, 2026

History-Aware RL Reduces Routing Violations in Dense Chip Layouts

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Researchers at New York University have presented a routing method that targets one of physical design’s most stubborn bottlenecks: detailed routing in dense layouts. In a technical paper titled “Routing Dense Layouts with History-Aware Offline Reinforcement Learning using LSTM,” they describe an offline reinforcement-learning policy that predicts iterative cost weights instead of relying only on conventional router heuristics.

The authors frame the problem as one of growing design-rule complexity. In dense operating conditions, modern routers can struggle to resolve persistent violations, especially when routing solutions become significantly harder to find. The proposed method is described as history-aware, meaning it incorporates prior routing context while selecting cost weights for each iteration.

According to the paper summary, the policy is built with an LSTM and uses readily available features from the router. The goal is to improve convergence across different placement densities, with particular attention to regimes where existing reinforcement-learning approaches have trouble because the routing search space is too difficult.

The work is presented as an attempt to make detailed routing more robust under high-density conditions, where repeated violations can dominate runtime. The paper is available as an arXiv preprint under the same title, authored by Afsara Khan and Austin Rovinski.

Source: Semiconductor Engineering

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