Researchers at Purdue University have published a paper on DRCdesign rule checkA verification step that checks whether layout geometries comply with fabrication rules.-Aid, a framework that automates local design-rule correction in IC1. integrated circuitIC is the common term for an integrated circuit.2. ion chromatographyAnalytical method that separates and identifies the components of a mixture. layouts. The approach is built around a closed-loop, verification-in-the-loop search process rather than a one-shot patching step, with the goal of fixing violations without changing the layout function.
According to the abstract, DRCdesign rule checkA verification step that checks whether layout geometries comply with fabrication rules.-Aid relies on an inference-time large language model inside an agentic framework. A deterministic Rule Engine converts violations reported by physical verification tools into a bounded menu of geometric edits, reducing the combinatorial search space that normally comes with layout repair. The paper describes this as a way to constrain the repair process to local changes.
The method explicitly targets local DRCdesign rule checkA verification step that checks whether layout geometries comply with fabrication rules. repair and uses repeated verification as part of the search loop. Instead of letting the model free-run over arbitrary geometry changes, the framework keeps the edits within the set defined by the rule engine, which is meant to preserve layout equivalence while addressing the flagged violation.
The work is presented as a technical paper titled “DRCdesign rule checkA verification step that checks whether layout geometries comply with fabrication rules.-Aid: Design-Rule Correction via Agentic Framework utilizing Inference-Time Large Language Models.” It was published as an arXiv preprint in July 2026.