AIartificial intelligence is not only increasing memory demand; it is changing how memory systems are built. As major suppliers continue to allocate more capacity and capital spending to HBM1. human body modelESD test model that simulates a person discharging static electricity into a component.2. High Bandwidth MemoryHBM is a stacked DRAM architecture designed to provide very high memory bandwidth. and advanced server memory, mature and specialty flash products are being squeezed. At the same time, larger models and inference workloads are pushing memory requirements into data tiering, movement and processing, making memory architecture a more central part of AIartificial intelligence system design.
Macronix is responding by expanding its NOR flash, NANDNot ANDA logic gate that outputs 0 when all inputs are 1, and outputs 1 in all other cases and eMMC portfolios toward higher densities, lower power consumption and greater reliability. The company has raised its 2026 capital expenditure to NT$37.8 billion to expand 12-inch wafer capacity and support demand for 3D NOR, NANDNot ANDA logic gate that outputs 0 when all inputs are 1, and outputs 1 in all other cases, eMMC and related products.
The market shift is especially visible in mature flash. Demand for NOR flash, SLCsurface laminar circuit NANDNot ANDA logic gate that outputs 0 when all inputs are 1, and outputs 1 in all other cases and eMMC is being supported both by higher shipments and by rising prices as supply remains constrained. Macronix expects the combined market for NOR flash, SLCsurface laminar circuit NANDNot ANDA logic gate that outputs 0 when all inputs are 1, and outputs 1 in all other cases and low-capacity eMMC of 32GB or less to reach about $24 billion in 2026, with NOR facing comparatively moderate price increases and SLCsurface laminar circuit NANDNot ANDA logic gate that outputs 0 when all inputs are 1, and outputs 1 in all other cases and eMMC under stronger supply pressure.
AIartificial intelligence servers are one of the clearest examples of the new demand pattern. NOR flash is used for boot, firmware, system control and security functions, and server designs now use more control components such as baseboard management controllers and network switches. That has pushed flash consumption per rack sharply higher, from roughly 600 to 800 devices in a previous-generation rack to more than 1,000 in the latest generation.
Beyond the volume effect, the company sees a deeper architectural change. HBM1. human body modelESD test model that simulates a person discharging static electricity into a component.2. High Bandwidth MemoryHBM is a stacked DRAM architecture designed to provide very high memory bandwidth. remains the fastest memory tier for training and inference, but its capacity and cost are becoming limiting factors. That is driving interest in memory tiers beyond HBM1. human body modelESD test model that simulates a person discharging static electricity into a component.2. High Bandwidth MemoryHBM is a stacked DRAM architecture designed to provide very high memory bandwidth., including high-bandwidth flash based on 3D NANDNot ANDA logic gate that outputs 0 when all inputs are 1, and outputs 1 in all other cases, high-speed interfaces and high-density packaging, as well as SSD1. Solid State Drivenon-volatile electronic storage medium, usually a hard disk drive in computers2. Solid-State DriveA non-volatile storage device used in the rack demo to hold full KV caches.-based architectures that can absorb data not required in HBM1. human body modelESD test model that simulates a person discharging static electricity into a component.2. High Bandwidth MemoryHBM is a stacked DRAM architecture designed to provide very high memory bandwidth..
For inference workloads, low-latency SLCsurface laminar circuit NANDNot ANDA logic gate that outputs 0 when all inputs are 1, and outputs 1 in all other cases is also being positioned to handle large volumes of random GPUgraphics processing unitA GPU is a parallel graphics processor widely used for AI acceleration. data accesses and improve GPUgraphics processing unitA GPU is a parallel graphics processor widely used for AI acceleration. utilization. The need is growing as KV cache expands with continuous conversation and task context in large language models and agentic AIartificial intelligence systems. Macronix has presented a dual-tier SSD1. Solid State Drivenon-volatile electronic storage medium, usually a hard disk drive in computers2. Solid-State DriveA non-volatile storage device used in the rack demo to hold full KV caches. architecture as a way to offload KV cache and distribute AIartificial intelligence workloads across different storage tiers.
Macronix is also advancing its technology roadmap. The company has 48-layer and 96-layer 3D NANDNot ANDA logic gate that outputs 0 when all inputs are 1, and outputs 1 in all other cases in mass production and is developing higher-layer-count devices. NOR flash is moving from 55 nm to 42 nm, with 3D NOR under development, while low-voltage flash is progressing from 3 V and 1.8 V toward 1.2 V for AIartificial intelligence, industrial and embedded systems.
Looking ahead, the company expects supply-demand conditions to remain tight into 2027, with qualification and yield ramp-up for new capacity taking two to three years or longer. Macronix will present its nonvolatile memory technologies and application solutions at electronica 2026 in Munich, including automotive electronics and edge AIartificial intelligence applications.