Researchers at the Technical University of Munich have published a neural-network-based transistor modeling approach aimed at speeding up SPICEsimulation program with integrated circuit emphasis simulation without sacrificing the precision needed in chip-design flows. The work focuses on a 3 nm nanosheet transistor and uses the trained models to predict drain current as well as multiple charge quantities.
The models were not only evaluated on isolated device behavior, but also inserted into standard cell library characterization, a task that requires thousands of SPICEsimulation program with integrated circuit emphasis runs and is therefore a demanding test of model consistency. The same approach was then exercised in analog- and digital-level simulations for more complex circuits.
Against an industry-standard Verilog-A-based compact model, the neural networks delivered accurate delay and power estimates while improving runtime and convergence behavior. The reported results include sub-0.11% error for delay and 0.76% error for total power across a wide range of circuits.
In standard cell library characterization, the neural-network models reduced simulation time by up to 8x compared with the conventional BSIM-CMG-based reference flow. That makes the approach relevant for workloads where large numbers of transistor simulations dominate the overall characterization effort.
The study also examines how neural-network size affects simulation precision and provides guidance on the trade-off between model complexity and accuracy. The overall result is a compact-model alternative that combines high-speed circuit evaluation with the numerical accuracy required for advanced-node characterization.