Researchers at the University of Alberta have presented PPAPlace, a placement optimization method that tries to predict post-route performance, power, and area directly from macro and standard-cell positions. The work targets a long-standing weakness of many placers: optimizing half-perimeter wirelength alone does not track final timing well, especially for post-route metrics such as worst negative slack and total negative slack.
The paper reports that recent benchmarking found almost no correlation between HPWL and post-route timing, and that six evaluated AIartificial intelligence placers actually worsened PPA1. power, performance, and areaPPA is the main optimization target for advanced-node designs.2. power, performance, area relative to a hierarchical baseline. To address this gap, the authors built a timing-driven differentiable surrogate that learns from post-global-routing labels rather than pre-route metrics. A label-fidelity study across ten circuits and four flow stages showed that post-global-routing labels offer the best compromise between final timing fidelity and the cost of generating training data.
Technically, PPAPlace uses a dual-stream predictor. One stream applies graph attention to the chip netlist, while the other uses spatial convolution on the placement grid. The model is trained to predict post-route WNS and TNS, and its gradients are propagated back to cell coordinates end to end. Those gradients are then used either as a co-objective inside an analytical placer, or as a refinement step that updates macro positions through projected gradient descent.
On five ChiPBench test circuits that were excluded from training, PPAPlace improved average WNS by 22% and TNS by 51% versus the hierarchical baseline, while keeping power and routability unchanged. The same predictor was used without retraining on the test circuits.