SK Hynix is working on a next-generation 3D DRAM1. dynamic random access memoryMemory technology or system for temporarily or permanently storing digital information.2. dynamic random-access memoryDRAM is a volatile memory technology architecture that separates the memory-cell processing area from the peripheral circuits that govern it. According to the report, the two parts would no longer be designed as one tightly coupled block, but as distinct functions that can be manufactured with different process technologies.
The key idea is process specialization. By decoupling the storage array from the control logic, SK Hynix can optimize the memory-cell portion for density and the peripheral circuitry for logic performance. That is a departure from classic DRAM1. dynamic random access memoryMemory technology or system for temporarily or permanently storing digital information.2. dynamic random-access memoryDRAM is a volatile memory technology design, where the integration of array and control functions is typically more unified.
This architectural split also changes the design requirements. The source says the approach calls for much deeper logic-design know-how than conventional DRAM1. dynamic random access memoryMemory technology or system for temporarily or permanently storing digital information.2. dynamic random-access memoryDRAM is a volatile memory technology development. In other words, 3D DRAM1. dynamic random access memoryMemory technology or system for temporarily or permanently storing digital information.2. dynamic random-access memoryDRAM is a volatile memory technology is not only a memory scaling effort, but also a move toward a more logic-intensive design flow for the peripheral functions.
The report does not describe the final manufacturing flow or production timing, but it makes clear that SK Hynix is pushing the concept of 3D DRAM1. dynamic random access memoryMemory technology or system for temporarily or permanently storing digital information.2. dynamic random-access memoryDRAM is a volatile memory technology beyond the traditional memory-cell-first model. The central technical shift is the separation of array and peripheral logic so each can be implemented with the most suitable technology.