SK hynix has detailed research on 3D FeNAND as a platform for analog compute-in-memory (A-CiM), positioning NANDNot ANDA logic gate that outputs 0 when all inputs are 1, and outputs 1 in all other cases for more than storage. The approach co-optimizes three layers of the architecture: the cell scheme, the non-cell interconnect and peripheral scheme, and the page scheme that determines how data is grouped and processed.
The motivation is the growing cost of moving data in large AIartificial intelligence models. By performing multiply-and-accumulate operations closer to memory, A-CiM reduces repeated transfers between storage and compute devices. In this design, 3D FeNAND is considered better suited than conventional charge trap nitride (CTNcharge trap nitrideCTN is the conventional 3D NAND cell structure used as the comparison baseline.) NANDNot ANDA logic gate that outputs 0 when all inputs are 1, and outputs 1 in all other cases because its ferroelectric material can support finer multi-level current control at lower power.
At the cell level, the work uses HZOhafnium zirconium oxideHZO is the ferroelectric material used to enable multi-level current control.-based ferroelectric material and domain switching to achieve gradual changes in current states. Instead of relying on conventional incremental step pulse programming alone, the method increases pulse number while keeping voltage largely unchanged, producing distinct current steps at the same read gate voltage. Four-level-per-cell operation in the low-current region and stable retention were demonstrated at the 300 mm wafer scale.
The non-cell optimization focuses on word line resistance and capacitance, both of which add switching overhead during A-CiM operation. A lower-resistance metal improved throughput by up to 16% and energy efficiency by up to 3%. Introducing air gaps in the oxide between word lines reduced parasitic capacitance by about 60%, lifting throughput by 1.2x and energy efficiency by 2x. Joint optimization raised throughput by up to 1.4x and energy efficiency by up to 2.2x.
At the page level, the study uses in-page pipelining (IPP1. inplane distortionGeometric distortion within the plane of a surface, such as a mask or wafer.2. in-page pipeliningIPP organizes layers within a page to reduce switching and improve parallelism.) to align data organization with AIartificial intelligence computation. By arranging neural network layers within a page and, where useful, replicating layers, IPP1. inplane distortionGeometric distortion within the plane of a surface, such as a mask or wafer.2. in-page pipeliningIPP organizes layers within a page to reduce switching and improve parallelism. reduces both MACmultiply-accumulateMAC is the basic operation used for AI inference and training workloads. operations and word line switching events. Simulations showed a twofold gain in energy efficiency and a ninefold gain in throughput versus the baseline architecture. Under the same chip-area constraints, the optimized 3D FeNAND architecture reached roughly 10 to 20 times higher throughput and around 4,000 to 5,000 times greater energy efficiency than conventional 3D arrays.