A new technical paper presents a physics-based system-technology co-evaluation flow for comparing A7A7 technology nodeA CFET design node used for the area comparison. CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices. and A10 nanosheet FETfield-effect transistorTransistor whose conduction channel is controlled by an electric field. technologies. The study does not stop at device characteristics, but tracks parasitics, thermal behavior, and aging all the way to chip reliability.
The authors link calibrated device models with optimized standard-cell generation and an automated GDS1. graphical design systemSoftware environment for creating technical designs and layouts graphically.2. graphical design softwareSoftware-related method or tool for development, control or data processing.3. Graphic Data SystemGDS is a data format for layout data in semiconductor design.4. Graphic Design SystemGDS is the final layout database format used for the benchmark’s physical output.-to-TCADtechnology computer-aided designSoftware-related method or tool for development, control or data processing. conversion chain. That enables accurate three-dimensional extraction of parasitic RCresistance-capacitanceElectrical property of a material or device that affects the relationship between current and voltage. effects, while a full RTL1. resistor-transistor logicSemiconductor device or transistor technology used to control electrical currents and signals.2. register transfer levelRTL is the hardware description layer where design assumptions are often captured.3. Register-Transfer LevelRTL describes the hardware implementation stage targeted by the benchmark.-to-GDS1. graphical design systemSoftware environment for creating technical designs and layouts graphically.2. graphical design softwareSoftware-related method or tool for development, control or data processing.3. Graphic Data SystemGDS is a data format for layout data in semiconductor design.4. Graphic Design SystemGDS is the final layout database format used for the benchmark’s physical output. implementation is used for an AIartificial intelligence accelerator design example. The flow also includes multiphysics thermal analysis and a physics-based evaluation of bias temperature instability aging.
According to the abstract, the same device model is used for both technology nodes. This makes it possible to isolate how much of the difference comes from parasitic RCresistance-capacitanceElectrical property of a material or device that affects the relationship between current and voltage.s and how much comes from design choices at different stages of the implementation flow. In other words, the comparison is structured to separate technology effects from flow-dependent effects.
The work was published by researchers from TU Munich, the University of Modena and Reggio Emilia, and Applied Materials. It frames A7A7 technology nodeA CFET design node used for the area comparison. CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices. and A10 NSFET as a case study for evaluating not only performance-related parasitics, but also thermal constraints and reliability aging within one unified methodology.