Synaptics says its Astra SR200 series marks a new step for microcontrollers by combining heterogeneous, AIartificial intelligence-native compute with integrated high-bandwidth custom DRAM1. dynamic random access memoryMemory technology or system for temporarily or permanently storing digital information.2. dynamic random-access memoryDRAM is a volatile memory technology scalable to hundreds of megabytes. The goal is to move larger AIartificial intelligence models and richer multimodal workloads from the cloud into an MCU1. microprocessor control unit2. mobile calibration unit3. microcontrollerA microcontroller is a compact integrated circuit designed to execute embedded control tasks in electronic systems. footprint.
The SR200 family pairs the Arm Cortex-M85 and Cortex-M52 cores, bringing together high-performance compute, low-power modes and edge-AIartificial intelligence acceleration on a single piece of silicon. Synaptics describes the devices as an xMCU, reflecting the idea of multiple compute dimensions in one chip.
At the top of the compute stack, the series integrates up to 400 GOPS of AIartificial intelligence acceleration, 256 MBmachine batch of custom DRAM1. dynamic random access memoryMemory technology or system for temporarily or permanently storing digital information.2. dynamic random-access memoryDRAM is a volatile memory technology, vision and audio capabilities, and hardware-rooted security. The design also incorporates Synaptics’s Torq NPUNeural Processing UnitA processor optimized for neural-network inference workloads. and Google Research’s Coral NPUNeural Processing UnitA processor optimized for neural-network inference workloads. to support CNN and transformer workloads.
A central element of the architecture is the tiered memory system. Instead of treating memory as a simple feed for CPUcentral processing unitMain processor that executes program instructions and performs data operations. and NPUNeural Processing UnitA processor optimized for neural-network inference workloads. blocks, the SR200 design builds high-performance compute around an on-chip memory architecture and adds a custom DRAM1. dynamic random access memoryMemory technology or system for temporarily or permanently storing digital information.2. dynamic random-access memoryDRAM is a volatile memory technology interface with in-package memory. Synaptics compares the result to bringing HBM1. human body modelESD test model that simulates a person discharging static electricity into a component.2. High Bandwidth MemoryHBM is a stacked DRAM architecture designed to provide very high memory bandwidth.-like memory behavior to a microcontroller.
The company says this memory structure is meant to solve two problems at once: feeding compute more efficiently and supporting ultra-low-power, always-on AIartificial intelligence processing. That is intended to make simultaneous handling of workloads such as always-on listening and contextual response possible within the device.
The SR200 line is divided into three pin-compatible tiers. SR210 targets power-optimized always-on voice and sensing with 200 GOPS. SR230 adds vision, display and optional audio at 300 GOPS for mainstream multimodal devices. SR250 delivers 400 GOPS with dual vision and display paths for more demanding edge applications.
Synaptics says the MCU1. microprocessor control unit2. mobile calibration unit3. microcontrollerA microcontroller is a compact integrated circuit designed to execute embedded control tasks in electronic systems.s are aimed at AIartificial intelligence wearables, battery-powered sensing devices, connected cameras, streamers and industrial vision-and-voice systems. The company says body-worn electronics are the strongest early traction area so far.