Traditional scan-based DFT1. design for testabilityDesign approach that makes circuits easier to test after manufacturing.2. design for testInclusion of test structures and design rules to make integrated circuits easier to test. flows are running into scaling limits as AIartificial intelligence and HPC1. High Performance ComputingCompute applications with particularly high performance demands, cited here as a driver for packaging and testing.2. high-performance computingHPC denotes compute-intensive chips that require advanced testing support. devices add more cores, more chiplets, and higher test coverage demands. The result is growing test data volume, tighter tester bandwidth constraints, routing complexity, and more difficult diagnosis. In this context, Synopsys is positioning TestMAX Unified Compression, based on DFTMAX SEQ, together with Streaming Fabric (SF) as a combined approach for next-generation AIartificial intelligence compute systems.
The key point is that compression alone is no longer enough. While unified compression reduces the amount of test data, the data still has to be distributed efficiently through the design. Streaming Fabric is described as a programmable, high-bandwidth delivery network that packetizes scan traffic and moves compressed test data through configurable hierarchical paths instead of relying on thousands of dedicated scan routes.
The article also emphasizes reuse across the silicon lifecycle. Modern AIartificial intelligence chips are expected to reuse test infrastructure during manufacturing, burn-in, system-level test, and in-field test. A unified codec can serve multiple phases and environments, which reduces implementation complexity while supporting test coverage and diagnosis. The approach is presented as a move away from separate compression hardware for each test stage.
Another shift is the move of test architecture development to RTL1. resistor-transistor logicSemiconductor device or transistor technology used to control electrical currents and signals.2. register transfer levelRTL is the hardware description layer where design assumptions are often captured.3. Register-Transfer LevelRTL describes the hardware implementation stage targeted by the benchmark.. According to the source, this enables earlier verification, earlier DRCdesign rule checkA verification step that checks whether layout geometries comply with fabrication rules. closure, and better consistency between RTL1. resistor-transistor logicSemiconductor device or transistor technology used to control electrical currents and signals.2. register transfer levelRTL is the hardware description layer where design assumptions are often captured.3. Register-Transfer LevelRTL describes the hardware implementation stage targeted by the benchmark. and implementation databases. That is intended to support a correct-by-construction flow and avoid expensive redesign iterations later in the project.
Synopsys frames the combined Unified Compression and Streaming Fabric approach as scalable from individual IP1. image placement2. Internet protocolInterface or communications concept for transmitting data between devices and systems.3. Intellectual PropertyIP denotes licensable semiconductor design blocks or technology elements. blocks to AIartificial intelligence accelerators with hundreds of millions of scan elements. The same message extends to the company’s TestMAX and STARsimultaneous transmitted and reflected Memory System (SMSSECS message service) IP1. image placement2. Internet protocolInterface or communications concept for transmitting data between devices and systems.3. Intellectual PropertyIP denotes licensable semiconductor design blocks or technology elements. family, which is presented as a foundation for cost-effective test solutions across the silicon lifecycle.