Backside power delivery opens a new routing option for advanced logic designs: thick, low-resistance metal layers can be placed on the back of the wafer, leaving the frontside interconnect stack less congested. A new study from the University of California, Santa Cruz examines how that extra freedom can be applied to clock distribution in 2 nm nanosheet-class devices.
The work focuses on backside clock meshes for 2 nm GAAFETGate-All-Around Field-Effect TransistorsThese transistors wrap the gate around the channel to improve electrostatic control. BSPDNbackside power delivery network technology. In conventional high-performance VLSIvery large-scale integrationIntegrated-circuit technology containing very large numbers of transistors on one chip., clock meshes are used to reduce skew and improve tolerance to on-chip variation, but they consume scarce premium metal resources. Moving part of the mesh to the backside changes that trade-off by using layers that are not fully occupied by the power grid.
At the same time, the architecture imposes a structural constraint: flip-flops remain on the frontside, so the backside mesh cannot drive them directly. Every connection must pass through a through-silicon via, which makes the distribution path more complex than in a purely frontside implementation. The study therefore examines the design space around this backside-to-frontside interface rather than treating it as a simple layout swap.
The authors report the first design-space exploration of this concept and implemented it in OpenROAD on GT2N, a 2 nm nanosheet technology. The result is a concrete look at how backside routing resources may be used beyond power delivery, with the clock network as the next candidate for backside integration in advanced node designs.