Semiconductor Engineering has added a new set of technical papers spanning device research, process integration, memory architecture, AIartificial intelligence serving, automotive networking, and verification methodology. The collection brings together several independent topics rather than a single platform announcement.
On the device side, one paper focuses on low-contact-resistance WSe₂ transistors, while another looks at backside clock meshes for 2nm GAAFETGate-All-Around Field-Effect TransistorsThese transistors wrap the gate around the channel to improve electrostatic control.s. Both topics point to continued work on reducing resistance and improving interconnect and clock distribution as device scaling moves deeper into advanced transistor architectures.
Memory research in the roundup includes row-parallel processing in DRAM1. dynamic random access memoryMemory technology or system for temporarily or permanently storing digital information.2. dynamic random-access memoryDRAM is a volatile memory technology, indicating interest in extracting more throughput from the memory array itself. In parallel, the list also includes HBF1. High Bandwidth FlashA NAND-based concept that combines storage capacity with higher bandwidth.2. High-Bandwidth FlashA memory concept under development that is intended to relieve bandwidth and capacity bottlenecks in AI inference systems. for high-throughput LLM1. local linear models2. Large Language ModelThe model class referenced in the long-context serving demo. serving, connecting semiconductor and system-level research with the compute demands of large language model deployment.
Two additional papers extend beyond core device and memory topics: a formal security analysis of CAN XL and work on abstraction and validation from physical devices to RTL1. resistor-transistor logicSemiconductor device or transistor technology used to control electrical currents and signals.2. register transfer levelRTL is the hardware description layer where design assumptions are often captured.3. Register-Transfer LevelRTL describes the hardware implementation stage targeted by the benchmark.. Together, the papers illustrate how current semiconductor research spans materials, architecture, system security, and verification methods across the stack.