ETH Zurich and NYU map power behavior in HBM2 DRAM chips

October 15, 2026

ETH Zurich and NYU map power behavior in HBM2 DRAM chips

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Researchers at ETH Zurich and New York University have published what they describe as the first comprehensive experimental characterization of power consumption in real HBM2 DRAM1. dynamic random access memoryMemory technology or system for temporarily or permanently storing digital information.2. dynamic random-access memoryDRAM is a volatile memory technology chips. The study uses measured chips rather than abstract models and focuses on how current draw changes with access type and data activity.

The results provide an empirical basis for building or validating HBM1. human body modelESD test model that simulates a person discharging static electricity into a component.2. High Bandwidth MemoryHBM is a stacked DRAM architecture designed to provide very high memory bandwidth. power models. The paper reports 13 new findings and 6 key takeaway messages, with two results standing out: read operations consume significantly more current than any other operation, and power varies strongly with data-pattern activity on internal buses.

In one highlighted case, toggling all HBM2 internal bank-group bus signals during a data transfer burst increased power consumption by 29.4% compared with keeping those signals constant. The work also shows that toggled data-bus signals during a burst materially affect current draw, reinforcing that HBM2 power behavior depends not only on the command being executed but also on the exact signal activity inside the memory stack.

Using these measurements, the researchers built an access pattern that raised average power consumption by 23.6% across 36 tested HBM2 chips compared with the highest-power-consuming JEDECJoint Electron Device Engineering CouncilJEDEC defines industry specifications and measurement loops for memory interfaces and devices.-specified current measurement loop. The study therefore extends beyond characterization and demonstrates a reproducible way to stress HBM2 chips more than the standard measurement sequence.

Overall, the paper links HBM2 power to structural and data-dependent effects inside the device and provides a measurement-backed baseline for future modeling work. Additional technical details were not included in the published summary.

Source: Semiconductor Engineering

More background: Fundamentals

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