imec has outlined new integration paths for CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices. devices that address two of the hardest manufacturing problems in next-generation logic: accessing the bottom transistor in a stacked structure and tuning threshold voltage without blowing up the thermal budget. The work targets CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices.s as a candidate continuation of the logic roadmap after GAAgate-all-aroundTransistor architecture with a circumferential gate. nanosheet transistors.
On the device side, imec says complementary FETfield-effect transistorTransistor whose conduction channel is controlled by an electric field. stacking can reduce standard-cell height to 3T and extend CMOS1. complementary metal-oxide semiconductorCircuit technology combining n- and p-channel MOS transistors for low static power consumption.2. complementary metal-oxide-semiconductorCMOS is a fundamental semiconductor technology for digital and analog circuits. scaling toward the A3 node. In this report, the focus is on modules that matter for both monolithic CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices.s and sequential CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices.s: a backside contact flow and a gate-stack approach that supports multiple Vt options in nanosheet and CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices. devices.
The backside-contact module is central because contacting the lower source/drain from the wafer backside improves access resistance and frees routing space on the front side. imec describes a revised scheme with an additional frontside-formed backside dielectric isolation structure under the source/drain, so the bottom SiGe:B epi is no longer seeded by the underlying Si substrate. According to the reported results, this improved the bottom pFET drive current by a factor of five, reduced access resistance from 1753 Ωµm to 378 Ωµm, and raised survival yield from 45% to 85% compared with the earlier flow.
The new contact flow still uses the usual backside steps, including wafer bonding, extreme thinning, and backside contact etch, but the frontside BDI changes the growth conditions before the backside module is completed. imec presents the process as generic enough to apply to both mCFET and sCFET devices.
For threshold-voltage control, imec moves away from the classic dipole-last approach, which relies on high-temperature annealing, and from dipole-first, which can damage the SiO2silicon dioxide interlayer during patterning. The proposed dipole-middle scheme deposits the shifter on a thin HfO2 layer, locks it in with a mild anneal, protects the interlayer during patterning, then completes the stack with a second HfO2 deposition and another anneal. On a CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices. test vehicle, this produced a consistent nFET Vt reduction of about 30 mV relative to the reference flow.