imec has disclosed new integration work for CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices. devices that addresses two of the main hurdles on the path beyond GAAgate-all-aroundTransistor architecture with a circumferential gate. nanosheet transistors: contacting the bottom device more efficiently and tuning threshold voltage without excessive thermal budget. The results come from imec’s latest logic roadmap and are tied to CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices.-specific development on the European NanoIC pilot line.
The first advance is an improved backside-contact module for stacked devices. Compared with a conventional flow in which backside dielectric isolation is formed only at the end of the process, imec adds a frontside-formed BDI structure beneath the source/drain region and combines it with a backside-formed BDI. This prevents the bottom SiGe:B source/drain epi from being seeded by the underlying Si substrate, which reduces variability and contact resistance. In the reported mCFET test vehicle, bottom pFET drive current improved fivefold, access resistance dropped from 1753 to 378 Wµm, and survival yield rose from 45% to 85%.
That module also comes with the expected process overhead for backside contacting, including wafer bonding, extreme substrate thinning, and backside contact etch. imec says the new scheme is believed to be generic enough to apply to sCFET devices as well. The improved isolation and access help lower resistance where the bottom device is most constrained, while also easing routing pressure on the frontside.
The second contribution is a gate-stack integration method for multiple threshold voltages. Instead of relying on gate-metal thickness changes, which are difficult in the tight spaces between stacked nanosheets, imec uses dipole-based Vt tuning with lanthanum. The new dipole-middle scheme places the shifter on a thin HfO2 layer, locks it in with a mild anneal, and then adds a second HfO2 layer. This protects the SiO2silicon dioxide interlayer during patterning and keeps the thermal budget below that of a dipole-last flow.
imec demonstrated the approach on a CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices. test vehicle and measured a consistent Vt reduction of about 30 mV for the accessible top nFETs versus a reference flow. Together, the two modules address backside contacting and multi-Vt integration with process sequences that are compatible with CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices. manufacturing.